Sharp Kabushiki Kaisha Corporation

Kunihiro Katayama

Yukihiro Yoshida

Noboru Kubo

Yasuki Kawasaka

Masayuki Shinagawa

Takumi Hashimoto

Yoshiaki Nakade

Tadashi Yoshikawa

An image data serial signal output from the parallel-serial converting circuitis converted into a differential amplitude signal by the LVDS transmitterin such a manner that the amplitude of the differential voltage of the image data parallel signal varies depending on the value of the synchronization code serial signal. Accordingly, the signal values of the synchronization code serial signal and the image data serial signal are simultaneously transmitted. On the reception side, the differential amplitude signal in which the amplitude of the differential voltage of the image data serial signal varies depending on the value of the synchronization code serial signal is received by the LVDS receiver. The signal values of the synchronization code serial signal and the image data serial signal are separated and output based on a predetermined comparison processing.

Data transmission apparatus, data reception apparatus, data transmission and reception apparatus and data transmission and reception method

A computer device includes a processor for processing an object code containing a plurality of instruction words. It further includes a memory for storing a plurality of pseudoinstruction words respectively corresponding to the plurality of instruction words. Preferably, the number of bits of each of the plurality of pseudoinstruction words is less than that of each of the plurality of instruction words. Finally, the computer device includes an instruction word converter for converting the pseudoinstruction word read out from the memory into an instruction word of the object code, and for outputting the instruction word obtained by the conversion to the processor.

Computer device and method for processing data utilizing

A test device which employs a scan path method includes a latch circuit for holding a scan in signal, a transfer gate connected between the scan in signal and an input terminal of the latch circuit and having a gate terminal receiving a clock signal, a select circuit for selecting one of a data signal and an output signal from the latch circuit in response to a mode select signal and for outputting the selected signal, and a flipflop circuit for holding an output signal from the select circuit in response to the clock signal and for outputting the held signal as a scan out signal.

Test device employing scan path having circuitry at switches between a

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Kyoto, Japan

Kunihiro Katayama