Kabushiki Kaisha Toshiba

Kunihiro Kasai

Hisato Oyamatsu

Fumitomo Matsuoka

Kazunari Ishimaru

Masahiro Inohara

Hirohisa Kawasaki

Yasunori Okayama

Masahiko Matsumoto

Takeo Nakayama

Yasuhiro Fukaura

A semiconductor device manufacturing method is disclosed. The method is to form a second semiconductor layer which has less susceptibility to adopting insulative characteristics than a first semiconductor layer on the first semiconductor layer. Then, grooves which expose portions of the second and first semiconductor layers are formed to extend from the upper surface of the second semiconductor layer into the first semiconductor layer. Next, portions of the first and second semiconductor layers which are exposed to the grooves are changed into an insulator form to fill the grooves with the insulator-form portions of the first semiconductor layer.

Semiconductor device manufacturing method

A semiconductor device includes a middle inter-level insulating film disposed on or above a semiconductor substrate, a conductive layer disposed on the middle inter-level insulating film, and an upper inter-level insulating film disposed on the middle inter-level insulating film and the conductive layer. The upper inter-level insulating film includes first, second, and third wiring grooves distant from each other. The second and third wiring grooves use the conductive layer as their bottoms. The side surfaces of the first, second, and third wiring grooves are covered with in-groove barrier layers. First, second, and third wiring layers are buried in the first, second, and third wiring grooves. The first, second, and third wiring layers are derived from the same wiring film, and have a thickness larger than that of the conductive layer. The second and third wiring layers are electrically connected to the conductive layer.

Semiconductor device and manufacturing method thereof

Semiconductor wafer, method of manufacturing the same and semiconductor device

The present invention is a semiconductor device having an element isolation structure of STI, in which after the formation of the STI trench, a silicon nitride film is left over only on the side wall portion of the trench, to form a side wall. Further, ions are implanted from the bottom surface of the trench on which the side wall is formed, and thus a high-concentration punch-through suppression region having the same conductivity as that of the substrate (or well) and a concentration higher that the impurity concentration of the other section close to the substrate (or well), is formed selectively only in the section of the substrate (or well) which is near the bottom surface of the trench. In this manner, the punch-through suppression region can be formed only in the bottom portion of the STI in a self-alignment manner by the thickness of the side wall. With this structure, even if the STI has a shallow or fine element isolation structure, the punch-through between diffusion layers can be suppressed, and the occurrence of a junction leak between the high-concentration diffusion layer region and the well can be prevented. Therefore, a well structure of a low capacitance, which is suitable for a high-speed operation device, can be designed.

Semiconductor device having buried-type element isolation structure and method of manufacturing the same

The present invention is a semiconductor device having an element isolation structure of STI, in which after the formation of the STI trench, a silicon nitride film is left over only on the side wall portion of the trench, to form a side wall. Further, ions are implanted from the bottom surface of the trench on which the side wall is formed, and thus a high-concentration punch-through suppression region having the same conductivity as that of the substrate (or well) and a concentration higher that the impurity concentration of the other section close to the substrate (or well), is formed selectively only in the section of the substrate (or well) which is near the bottom surface of the trench. In this manner, the punch-through suppression region can be formed only in the bottom portion of the STI in a self-alignment manner by the thickness of the side wall. With this structure, even if the STI has a shallow or fine element isolation structures the punch-through between diffusion layers can be suppressed, and the occurrence of a junction leak between the high-concentration diffusion layer region and the well can be prevented. Therefore, a well structure of a low capacitance, which is suitable for a high-speed operation device, can be designed.

A gate electrode is formed in an element region of a semiconductor substrate. By ion implantation using the gate electrode as the mask, a low density doping (LDD) region is formed. By ion implantation after forming a side wall insulating film on the side wall of the gate electrode, source and drain regions are formed. Afterwards, by varying the thickness of the side wall insulating film of the side wall of the gate electrode, that is, by reducing the thickness of the side wall insulating film, a sufficient silicide region is formed on the source and drain regions. A silicide layer is formed on the gate electrode and source and drain regions by thermal reaction between a refractory metal and silicon in the gate electrode or in the semi-conductor substrate.

Manufacturing method of MOSFET having salicide structure

A method for manufacturing a surface mounting type semiconductor device, to prevent a bump from forming on a test pad, by contacting with a probe needle at a die sort test in manufacturing a surface mounting type semiconductor device. A test pad is formed with a layer, made of the same components as a bonding pad, above the major surface of semiconductor substrate, where an IC is formed. A probe needle is applied onto the test pad to carry out a die sort test. Subsequently, for a conforming article, a resist film is patterned by a lithography technique, thus removing only the test pad. A bump is normally formed only on the remaining bonding pad, thereby avoiding a continuity failure at assembly and any unexpected short-circuits during the connection with the wiring.

Method of manufacturing semiconductor device having a test pad

A thin film transistor includes a semiconductor thin film formed with a source region and a drain region at opposite end portions thereof and having an offset region near at the drain region, a gate electrode formed above the region between the source region and the offset region of the semiconductor thin film, with a gate insulating film being interposed, and a conductive layer formed above the gate electrode or under the semiconductor thin film, with an insulating film being interposed, the conductive layer being applied with generally the same potential as the gate electrode, wherein the resistance value of the offset region is controlled by the potential of the conductive layer. The gate electrode may be formed under the semiconductor thin film. In this case, the conductive layer is formed above the semiconductor thin film or under the gate electrode, with an insulating film being interposed. An SRAM is also provided which uses a thin film transistor constructed as above.

Growing community of inventors

Yokohama, Japan

Kunihiro Kasai