Adv Antest Corporation

The University of Tokyo

Thine Electronics, Inc.

Aika Design Inc.

Kunihiro Asada

Toru Nakura

Satoshi Komatsu

Masahiro Ishida

Takahiro Yamaguchi

Satoshi Miura

Tetsuya Iizuka

Yoshimichi Murakami

James Sumit Tandon

Shuhei Yamamoto

Shunichi Kubo

Takashi Kusaka

Naoki Terao

Rimon Ikeno

Yohei Ishizone

Norihito Tohge

A power supply apparatus supplies a power supply voltage V. The power supply apparatus includes a compensation circuit in addition to a main power supply. The compensation circuit receives, via its input, as a feedback signal, a detection signal Vthat corresponds to the power supply voltage V. The compensation circuit has input/output characteristics fthat correspond to the characteristics of the main power supply and the characteristics of a target power supply to be emulated. The compensation circuit injects or otherwise draws a compensation current ithat corresponds to the detection signal Vto or otherwise from a node for generating the power supply voltage V.

Power supply apparatus

This embodiment relates to a clock data recovering apparatus capable of improving consecutive identical digits (CID) resistance. The clock data recovering apparatus includes a clock generating apparatus. The clock generating apparatus includes a signal selection unit, a phase detection unit, a phase control unit, a selection unit, a phase delay unit, a time measurement unit, and a phase selection unit. The phase delay unit includes a plurality of delay elements. The phase selection unit selectively outputs an output signal of any one of the plurality of delay elements as a feedback clock. The phase detection unit detects a phase relation between an edge signal and the feedback clock. The phase control unit outputs a control signal to control a signal selection operation by the phase selection unit such that a phase difference detected by the phase detection unit decreases, to the phase selection unit.

Clock generating apparatus and clock data recovering apparatus

A judgment unit judges the pass/fail of DUTs. A power supply circuit has changeable characteristics, and supplies a power supply signal to the DUTs. A condition setting unit performs a pilot test before a main test for the DUTs, and acquires a test condition to be used in the main test. The condition setting unit executes: (a) measuring a first device characteristic value for each of multiple pilot samples sampled from among the DUTs while emulating a power supply characteristic close to what is used in a user environment in which the DUT is actually used; (b) measuring a predetermined second device characteristic value for each of the multiple pilot sample devices while emulating a power supply characteristic close to what is used in a tester environment in which the main test is performed; and (c) determining the test condition based on the first and second device characteristic values.

Test apparatus

Provided is a detection apparatus that detects process variation in a plurality of comparators that each output a comparison result obtained by comparing a signal level of an input signal to a reference level, the detection apparatus comprising a signal input section that inputs the input signal and the reference level in common to the comparators, and sequentially changes the signal level of the input signal; and a detecting section that detects, for each signal level, a number of comparison results that indicate a predetermined result, from among the comparison results of the comparators, and detects the process variation based on a distribution of the number of comparison results that indicate the predetermined result.

Detecting apparatus, wafer and electronic device

A signal conversion circuit, a PLL circuit, a delay control circuit and a phase control circuit for promoting miniaturization and for reducing quantization noise. TSTC does not require a low-pass filter of capacitor Cm with large layout area conventionally required for converting pulse width to voltage, which promotes miniaturization and cost reduction. TSTCgenerates analog voltage adequate for transition state at boundary where pulse signal transits, which reduces quantization noise, compared with conventional digital PLL circuits.

Signal conversion circuit, PLL circuit, delay adjustment circuit, and phase control circuit

A clock data recovery devicegenerates a recovered clock Recovered Clock and recovered data Recovered Data based on an input signal Data In, and includes a signal selector, a phase delay unit, a time measurement unit, a phase selector, an edge detector, a polarity detector, a logic inverter, and a data output unit. The signal selector, the phase delay unit, the time measurement unit, and the phase selectorconstitute a clock-generation deviceA. The phase delay unitincludes a plurality of cascaded delay elementsto. The phase selectorselects a signal output from the delay element in a position corresponding to a unit interval time among the delay elementsto, and outputs the signal as a feedback clock Feedback Clock.

Clock-generating device and clock data recovery device

Provided is a measurement apparatus that measures an input signal, comprising a plurality of first comparators that each receive the input signal, have a common first reference level set therein, and compare a signal level of the input signal to the first reference level; and a level-crossing timing detecting section that detects a level-crossing timing at which the signal level crosses the first reference level, based on comparison results of the first comparators.

Growing community of inventors

Tokyo, Japan

Kunihiro Asada