Nippon Electric Co., Ltd.

Nec Corporation

Kunihiko Niwa

Akira Kanemasa

Atsushi Tomozawa

Shinichi Aikoh

An echo canceller for cancelling echoes which result from impedance mismatching in a two-wire/four-wire conversion circuit. The prior art employed an input terminal, an output terminal, a transmitter section, a receiver section, a digital-to-analog converter, an adaptive digital filter, a subtractor, a sample hold circuit, an analog-to-digital converter, a multiplier, a low pass filter, a hybrid circuit, and a two-wire communication path, for the purpose of generating a replica of the echo signal to cancel such echos. A method has also been proposed which employs a polarity discriminator circuit instead of an analog-to-digital converter, and utilizes approximation algorithms to correct an adaptive digital filter tap coefficient using the signs of an error signal. In order to carry out this alternative method, the invention employs a fast convergence system comprising a circuit for generating an echo replica in response to a transmit signal, a circuit for producing a difference signal by subtracting the echo replica from a signal which contains a receiver signal and echo, a circuit for multiplying and averaging the difference signal and a polarity of the echo replica, a circuit for absorbing a fluctuation in an absolute value of the averaged output, and a circuit for adaptively varying a tap correction amount of a filter of the echo canceller in response to an output of the fluctuation absorbing circuit.

Fast convergence method and system for echo canceller

In a digital time division multiplexed telephone transmission system, a plurality of telephone signals are cyclically sampled and quantized so that each sampled value may be encoded into a binary codeword of a preset number of bits and that a series of codewords equal in number to the telephone signals may constitute a frame and a series of a predetermined number frames may in turn constitute a superframe. At the transmission end, an input circuit (202) receives the time division multiplexed telephone signals, and a code converter (204) coupled to the input circuit and responsive to a state-representing signal successively converts each of the binary codewords into a plurality of modified codewords. The modified codewords are variably assigned comparatively smaller and greater numbers of binary digits depending on the state-representing signal, the comparatively greater number being equal to or smaller than the preset number. A selection circuit (207) is supplied with the modified codewords and selectively allows one of the modified codewords to pass. A bit-number-assigning circuit (205) is coupled to the code converter and responsive to the output of the selection circuit to produce the state-representing signal in response to the corresponding one of at least one preceding frame, and for each of the modified codewords, the bit-number-assigning circuit produces a bit-number-representing signal indicating the number of bits assigned to the binary codeword being transmitted. A multiplexer (206) is coupled to the bit-number-assigning circuit and arranges in time domain the output of the selection circuit, bit-number-representing signal and a superframe synchronization signal. At the reception end, a code-inverse converter (1003) is responsive to the bit-number-representing signal to reproduce the binary codewords from the modified codewords.

Time division multiplexed transmission systems for telephone or like

An arithmetic unit for performing the operation of multiplying input data by successive powers of a constant and accumulating the products represented by ##EQU1## WHERE .alpha. IS A CONSTANT, IS DISCLOSED. The arithmetic unit includes a recursive path which does not necessitate a multiplier, and operations which really necessitate multiplication are carried out only when the input data have substantially entered this recursive path thereby substantially reducing the number of multiplications required. The arithmetic unit has particular application in performing DFT (Discrete Fourier Transform) or IDFT (Inverse Discrete Fourtier Transform).

Arithmetic unit for DFT and/or IDFT computation

An FFT processing unit of simplified construction comprises one or more arithmetic stages serially connected. Each stage has a plurality of recursive arithmetic paths each consisting of a delay element, a simplified multiplier for multiplying by .+-.1 and .+-.j where j = .sqroot.-1, and an adder. The adder is supplied with a serial input digital data series and the output is provided to the delay element and multiplier connected in series. A switch successively selects the output signals obtained from the plurality of recursive arithmetic paths. A second multiplier multiplies the signals selected by the switch by predetermined coefficients.

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Tokyo, Japan

Kunihiko Niwa