Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Microcomputer Engineering, Ltd.

Other

Renesas Technology Corp.

Kunihiko Nakada

Takashi Endo

Takashi Tsukamoto

Masahiro Kaminaga

Yasushi Akao

Takashi Watanabe

Yuuichirou Nariyoshi

Takeshi Miyazaki

Shiro Baba

Haruo Keida

Hajime Yasuda

Hisao Sasaki

Yoshiyuki Miwa

Hiroshi Watase

Chiaki Tanimoto

Tsuyoshi Jouno

Masaru Ohki

Yasuko Fukuzawa

Nobutaka Nagasaki

Masatoshi Takahashi

Chiaki Terauchi

Satoshi Taira

Shigeo Hirabayashi

A malfunction detection system is provided that can continue or terminate processing appropriately even if a malfunction occurs in an information processing unit. In this regard, the information processing unit receives branch direction information, carries out a conditional branch depending on the branch direction information, and performs an applicable operation on data I. At this time, the information processing unit performs an applicable operation on data J, other than the operated data I, in the conditional branch path and outputs the result for examination, thereby enabling validation of the conditional branch.

Information processing unit having tamper-resistant system

An object of the present invention is to prevent secret information that is being internally processed from being inferred through operational information of a secured device, including the current consumption information. One solution is provided by an information processing device having at least a key generation apparatus that generates key data automatically, an encryption unit that encrypts data with the corresponding key data, a register that stores a plurality of encrypted data items with the corresponding encryption key data items, and an arithmetic unit that performs operations using data expressed with the corresponding encryption key data and new key data as the input, encrypts the operation result with new input key data, and outputs the result, thereby being capable of performing internal processing on an encrypted data expression. Accordingly, only encrypted data is transferred on the internal or external data bus line.

Information processing device

It is a technological object of the present invention to provide an information processing device, a card and a card system that have a high level of security. In order to achieve the object described above, the present invention provides a data processing apparatus comprising at least a first information processing device and a second information processing device connected to the first information processing device by a signal line, the data processing apparatus having a means for changing power consumption on the signal line during transmission of a signal through the signal line in accordance with an actual state of the power consumption that would be observed when the means were not used. Furthermore, the present invention also provides another data processing apparatus comprising at least a first information processing device and a second information processing device connected to the first information processing device by a signal line wherein, between at least either the first information processing device or the second information processing device and the signal line, a signal from the first information processing device or the second information processing device can be encrypted and a signal received from the signal line can be decrypted. In addition, the present invention also provides a further data processing apparatus comprising at least an information processing device, an information memory device and a signal line connected at least to the information processing device wherein at least in an operation to store information into the information memory device, the information is encrypted, and information stored in the information memory device can be decrypted.

Information processing device, card device and information processing system

Disclosed herein are an IC card and a microcomputer which have implemented the strengthening of security and the speeding up and enhancement of signal processing for the security. In an IC card, which is supplied with an operating voltage by an electrical connection between each of external terminals and a read/write device, and includes an input-output operation of data with an encoding process or a decoding process, a disturbance-aimed processing operation is included in the encoding process or decoding process to uniformalize timings provided to operate an internal circuit and its operating current. In a microcomputer having a module configuration including an input-output operation of data with an encoding process or a decoding process, a disturbance-aimed processing operation is included in the encoding process or decoding process to uniformalize timings provided to operate an internal circuit and its operating current.

IC card and microprocessor

In a microcomputer incorporating a microprocessor, the coprocessor having product-sum operation arithmetic units executes residue multiplications given by 'A=A.multidot.B.multidot.R.sup.-1 mod N+kN', 'A=A.sup.2 .multidot.R.sup.-1 mod N+kN' and 'A=A.multidot.R.sup.-1 mod N 30 kN' and is provided with a multiplication function of executing a preprocessing 'R.sup.2 mod N' at high speed. It is possible to perform a power-residue operation 'X.sup.Y mod N' at high speed by the microprocessor, using these calculation functions of the coprocessor.

Data processor and microcomputer

An output gate means is provided which is capable of outputting individual signals selectively to an internal bus; the individual signals are interchanged among a plurality of functional modules connected to the internal bus which is interfaced with an external circuit. An input gate means is provided which is capable of supplying selectively a signal, input to the internal bus, to a specified functional module in place of an individual signal.

Semiconductor integrated circuit device with test mode for testing CPU

A reception unit for providing data supplied from a serial input circuit to an inner bus and a transmission unit for providing the data supplied from the inner bus to a serial output circuit hold at least two sorts of control procedures among HDLC procedure, BI-SYNC procedure and start-stop synchronous procedure as control procedures for data transmission/reception, and the control procedures held by these units can be selected alternatively based on a command of the processor.

Integrated data processor having mode control register for controlling

A reception unit for providing data supplied from a serial input circuit to an inner bus and a transmission unit for providing the data supplied from the inner bus to a serial output circuit hold at least two types of control procedures selected from HDLC procedure, BI-SYNC procedure and start-stop synchronous procedure as control procedures for data transmission/reception, and the control procedures held by these units can be selected alternatively based on a mode control data written in a mode control register by a processor.

A data processor controller for a microprogramming system is constructed with a single operation execution unit serving both a microprocessor and a peripheral device such as a direct memory access controller. In addition to the single operation execution unit, the controller includes a micro-memory which stores micro-instructions for controlling both the microprocessor and the peripheral device, and address registers, multiplexers and decoders integrated into a single device. Different ROM address registers in the controller are separately assigned to provide an address decoder with addresses of selected memory locations in the micro-memory containing the micro-instructions for the microprocessor and the peripheral device, thereby enabling the controller, through multiplexing between the address registers, to use the arithmetic execution unit, counter and bus interface of the single operation exeuction unit on a time sharing basis, for controlling the functions of both the microprocessor and the peripheral device.

Integrated CPU and DMA with shared executing unit

Growing community of inventors

Koganei, Japan

Kunihiko Nakada