Yamaha Corporation

Kunihiko Mitsuoka

Masao Noro

Nobuaki H Tsuji

Takayuki Kamiya

Yasuhiko Sekimoto

Masamitsu Hirano

A method of manufacturing a CMOS-BJT semiconductor device comprises the steps of: forming a collector region of a first conductivity type and a first well of the first conductivity type, simultaneously in a semiconductor substrate; forming a second well of a second conductivity type opposite to said first conductivity type, in the semiconductor substrate; forming a base region of the second conductivity type in the collector region; forming first and second insulated gate structure on said first and second wells, and a junction protection structure having same constituent elements as said insulated gate structures on said base region; and forming second source/drain regions of the first conductivity type in said second well, and an emitter region of the first conductivity type in the base region, simultaneously, with an emitter-base junction reaching the principal surface below said junction protection structure.

Semiconductor device including bipolar junction transistor with protected emitter-base junction

An input signal (SIN) is inverted by an inverter (), and the inverted input signal is entered into a tri-state type inverter (). An output portion of this inverter is connected via a delay path () to an input portion of an operational amplifier (). This operational amplifier owns a hysteresis characteristic with respect to a signal entered thereinto. An exclusive-OR gate circuit () controls to set the output state of the inverter to a low impedance state upon receipt of a signal (S) obtained by inverting the input signal, and controls to set the output state of the inverter to a high impedance state upon receipt of a signal (S) output from the operational amplifier. As a result, an amplitude of a signal (S) is limited to a constant amplitude in response to the hysteresis characteristic of the operational amplifier (), and a delay time is made constant.

Delay circuit

An operational amplifier has a differential amplifier stage comprising a pair of first PMOS transistors for inputting signals, which are arranged between a positive voltage supply coupled with a first constant current source and a negative voltage supply, wherein second PMOS transistors of a high voltage resistant type, gates of which are biased to a prescribed voltage, are arranged on current paths lying between the first PMOS transistors and the negative voltage supply together with load resistors. Herein, each of drain voltages of the first PMOS transistors is limited to a certain value that is higher than the prescribed voltage by a gate threshold voltage. Therefore, even when the first PMOS transistors are configured of a normal voltage resistant type, it is possible to reliably prevent voltages applied to the first PMOS transistors from exceeding breakdown voltages thereof, thus avoiding unnecessary reduction of an S/N ratio.

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Iwata, Japan

Kunihiko Mitsuoka