Sigma Corporation

Kunihiko Kanda

Kaoru Kanda

A method for detecting an endpoint of development including the steps of; forming a resist layer on a conductive layer formed on a substrate; exposing the resist layer by using light, X-rays, or electron beams; forming one electrode by connecting a connector consisting of a first conductive material to the conductive layer through the exposed resist layer on the substrate; forming another electrode by dipping an assembly consisting of a second conductive material into a developing solution; and developing the exposed resist layer while monitoring the current flowing between two electrodes.

Method for detecting endpoint of development

A method for forming a electrical interconnections, according to the invention, comprises forming number of semiconductor circuit elements on one semiconductor substrate, depositing an electrically conductive layer on substantially the entire surface of the semiconductor substrate, etching the electrically conductive layer patterned by the photolithography, for example, coating a photoresist on the electrically conductive layer, placing a mask of a pattern of electrical connecting lines on the photoresist-coated conductive layer and exposing the assembly to actinic rays to effect a development treatment, then placing one electrode composed of the electrochemically same material as that of the electrically conductive layer so that at least one point of said one electrode is brought into contact with the electrically conductive layer, dipping the assembly in an etching solution while using as the other electrode an electric conductor composed of a material electrochemically different from the material of the electrically conductive layer, performing wet chemical etching of the electrically conductive layer while measuring an electric current flowing between the two electrodes, and terminating etching of the electrically conductive layer when said current largely decreases or continuing etching for a certain time after said current largely decreases and is reduced below a timely determined level whereby electrical interconnections are formed for the respective semiconductor circuit elements on the semiconductor substrate.

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Yokohama, Japan

Kunihiko Kanda