Rohm Co., Ltd.

Renesas Technology Corp.

Horiba, Ltd.

Hitachi-kokusai Electric Inc.

Kabushiki Kaisha Toshiba

Renesas Electronics Corporation

National Institute of Advanced Industrial Science and Technology

Kunihiko Iwamoto

Toshihide Nabatame

Koji Tominaga

Bungo Tanaka

Michihiko Mifuji

Tetsuji Yasuda

Arito Ogawa

Yuuichi Kamimuta

Sachito Horiuchi

Naohiro Nomura

Tomoaki Nishimura

Tsuyoshi Horikawa

Hiroyuki Ota

Akira Toriumi

Takatoshi Manabe

A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.

Semiconductor device with different material layers in element separation portion trench and method for manufacturing semiconductor device

An integrated circuit having a plurality of miniaturized transistors, wherein the plurality of transistors include: high concentration transistors which include channel regions having impurity concentrations of a first concentration; and low concentration transistors which include channel regions having impurity concentrations of a second concentration lower than the first concentration.

Integrated circuit and method of manufacturing integrated circuit

A differential circuit includes a differential pair and a back gate bias circuit. The differential circuit includes a first MOS transistor and a second MOS transistor provided between a first power supply line, to which a first power supply voltage is applied, and a second power supply line, to which a second power supply voltage is applied. The back gate bias circuit applies a bias voltage closer to the first power supply voltage than source potentials of the first MOS transistor and the second MOS transistor to back gates of the first MOS transistor and the second MOS transistor.

Differential circuit

Non-volatile memory cell in semiconductor device

Method of manufacturing non-volatile memory cell with simplified step of forming floating gate

A semiconductor device manufacturing method includes the steps of forming a silicate film by performing a first step of forming a metal oxide film on a silicon substrate, and a second step of inducing a solid phase reaction between the metal oxide film and a surface of the silicon substrate by heat treatment, and forming a high dielectric constant insulating film on the silicate film.

Semiconductor device manufacturing method

After forming a pure silicon oxide film on respective surfaces of an n-type well and a p-type well, an oxygen deficiency adjustment layer made of an oxide of 2A group elements, an oxide of 3A group elements, an oxide of 3B group elements, an oxide of 4A group elements, an oxide of 5A group elements or the like, a high dielectric constant film, and a conductive film having a reduction catalyst effect to hydrogen are sequentially deposited on the silicon oxide film, and the substrate is heat treated in the atmosphere containing H, thereby forming a dipole between the oxygen deficiency adjustment layer and the silicon oxide film. Then, the conductive film, the high dielectric constant film, the oxygen deficiency adjustment layer, the silicon oxide film and the like are patterned, thereby forming a gate electrode and a gate insulating film.

Semiconductor device and manufacturing method of the same

CMISFETs having a symmetrical flat band voltage, the same gate electrode material, and a high permittivity dielectric layer is provided for a semiconductor device including n-MISFETs and p-MISFETs, and a fabrication method thereof, the n-MISFETs including: a first metal oxide layer, placed on the 1st gate insulating film, having a composition ratio shown with M1M2O (where M1=Y, La, Ce, Pr, Nd, Sm, Gd, Th, Dy, Ho, Er, Tm, Yb or Lu, M2=Hf, Zr or Ta, and x/(x+y)&#x3e;0.12); a second metal oxide layer; and a second metal oxide layer, the p-MISFETs including: a second gate insulating filmplaced on the surface of the semiconductor substrate; a third metal oxide layer, placed on the 2nd gate insulating film, having a composition ratio shown with M3zM4wO (M3=Al, M4=Hf, Zr or Ta, and z/(z+w)&#x3e;0.14); a fourth metal oxide layer; and a second conductive layerplaced on the fourth metal oxide layer

Semiconductor device and fabrication method thereof

A method of manufacturing a metal compound thin film is disclosed. The method may include forming a first metal compound layer on a substrate by atomic layer deposition, performing annealing on the first metal compound layer in an atmosphere containing a nitrogen compound gas, thereby diffusing nitrogen into the first metal compound layer, and forming a second metal compound layer on the first metal compound layer by atomic layer deposition.

Semiconductor device, method of manufacturing the same, and method of manufacturing metal compound thin film

After the surface of the substrate is cleaned, an interface layer or an antidiffusion film is formed. A metal oxide film is built upon the antidiffusion film Annealing is done in an NHatmosphere so as to diffuse nitrogen in the metal oxide film. Building of the metal oxide film and diffusion of nitrogen are repeated several times, whereupon annealing is done in an Oatmosphere. By annealing the film in an Oatmosphere at a temperature higher than 650&#xb0; C., the leak current in the metal oxide film is controlled.

Metallic compound thin film that contains high-k dielectric metal, nitrogen, and oxygen

Method of fabricating a metal oxynitride thin film that includes a first annealing of a metal oxide film in a nitrogen-containing atmosphere to form a metal oxynitride film and a second annealing of the metal oxynitride film in an oxidizing atmosphere

A metal oxide thin film may be obtained by providing a source gas and an oxidizer gas. The source gas may include a hydrolyzable metallic compound. The oxidizer gas may include a hydrate of a metal salt. The metal oxide thin film may be obtained by alternately feeding the source gas and the oxidizer gas into a reaction chamber in which a substrate is placed.

Metal thin film and semiconductor comprising a metal thin film

To provide a semiconductor device that enables to suppress a defect density of a gate insulating film of an MISFET, gain a sufficient electric characteristic thereof, and make an Equivalent Oxide Thickness (EOT) of the gate insulating film 1.0 nm or less. The MISFETs are formed to have the gate insulating film formed on a main surface of a silicon substrate, and a gate electrode formed on the gate insulating film, wherein the gate insulating film includes a metal silicate layer formed by a metal oxide layer and a silicon oxide layer and the metal silicate layer is formed so as to have concentration gradients of metal and silicon from a silicon substrate side toward a gate electrode side.

Semiconductor device and manufacturing method thereof

A metal atomic layer and an oxygen atomic layer are formed in this order by ALD, followed by rapid heating through RTA (Rapid Thermal Annealing). This cycle of steps is repeated to form a high dielectric constant film.

Film formation apparatus

A high dielectric gate insulating film having the structure that a high-nitrogen layer, a low-nitrogen layer, and a high-nitrogen layer are layered in this order from a silicon-substrate side.

Growing community of inventors

Kyoto, Japan

Kunihiko Iwamoto