Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Socionext Inc.

Kunihiko Hayashi

Tetsuya Tanaka

Nobuo Higaki

Tokuzo Kiyohara

Hideshi Nishida

Kozo Kimura

Hiroshi Kadota

Kazuya Furukawa

Kazushi Kurata

Shigeki Fujii

Toshio Sugimura

Akihiro Miyazaki

Kengo Nishimura

Satoshi Ikawa

Kazuyuki Uchida

Jyunichi Nakahashi

Motohide Nishibata

Yuki Kitamura

A processor executes a plurality of tasks by switching a timeslot and iterating a plurality of timeslots. The processor includes a table in which tasks are defined in correspondence with timeslots. In the table, the number of timeslots to be held in one iteration is defined, for each of the timeslots a total time period during the predetermined number of iterations is designated, and a plurality of tasks are defined in correspondence with at least one of the timeslots. A timeslot is switched every time a predetermined period elapses. One task is selected and executed by referring to the table in correspondence with switching of timeslot.

Processor and program execution method capable of efficient program execution

A cache control apparatus according to the present invention includes a cache allocation control unit which allocates each of a plurality of ways included in a cache memory to one or more of tasks to be executed by a plurality of processors. In the case where a group of ways includes an unallocated way that is not allocated to any of the tasks and a way allocated to one or more of the tasks which is to be executed by one of the processors, the cache allocation control unit allocates the unallocated way included in the group to the one or more of the tasks to be executed by the one of the processors.

Cache control apparatus, and cache control method

A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

Provided is a program control device which switches, per timeslot, between threads to be executed. The program control device includes: a first interrupt creation unit which creates a first interrupt signal which designates a timeslot as a destination; and a first receiving unit which [i] does not receive the first interrupt signal if the timeslot as the destination is not a current timeslot, and [ii] receives the first interrupt signal if the timeslot as the destination is the current timeslot.

Program control device including per-timeslot switching of thread execution

A task execution method for executing a plurality of tasks while switching the tasks from one to another by time-sharing, wherein an allocated time is allocated for each of the plurality of tasks, and the plurality of tasks includes a plurality of first-type tasks and a single second-type task, and the task execution method includes a task selection step which selects a task from among the plurality of tasks according to a predetermined sequence, a correction step which corrects an allocated time for the second-type task so that execution of the plurality of tasks completes within the cycle time, when the task selected is a second-type task, which is the total allocated time for the plurality of tasks, and a task execution control step which causes the selected task to be executed so that the execution of the selected task completes within the allocated time or the corrected allocated time.

Task execution device and method

A method of assigning task management blocks for first type tasks to time slot information on a one-by-one basis, assigning a plurality of task management blocks for second type tasks to time slot information, selecting a task management block according to a priority classification when switching to the time slot of the time slot information, and switching to the time slot except the time slot information. Additionally a task switching apparatus selects the task management block assigned to the time slot and executes the task.

Task switching based on assigned time slot

Apparatus for switching the task to be completed in a processor by switching to the task assigned time slot

A program conversion device for converting a program source is provided. The program conversion device comprises: a section and index acquisition device for acquiring a section code for indicating a section embedded in the program and performance index information embedded in the program in association with the section code; a task code conversion device for separating the acquired section code into task codes and adding a code to indicate the beginning of the task and a code to indicate the end of the task; and a task index attachment device for attaching a performance index, to input to the scheduler, to the task.

Program conversion device and method

In synchronization of a conventional AV system, when a stream as the master stops, a system clock cannot be corrected for synchronization. Since the correction is consistently performed even when an error is small, overhead of correction is large. On the other hand, when an error is large, sharp correction causes a feeling that something wrong. In the present invention, when the stream as the master stops, previously registering the degree of priority regarding the master, consideration of a corrected period or a previous error for the system clock, or transmitting a stream containing information regarding the master can allow for other process to serves as the master. Accordingly, it is possible to provide a method for synchronization with maintaining correction of the system clock. When a corrected error is large, gradual correction or reference can provide a system with normal feeling. Furthermore, when an error of correction is small, omission of correction or reference can provide a system with less overhead.

AV synchronization system

A method of assigning task management blocks for first type tasks to time slot information on a one-by-one basis, assigning a plurality of task management blocks for second type tasks to time slot information, selecting a task management block according to a priority classification when switching to the time slot of the time slot information, and switching to the time slot except the time slot information. Additionally, a task switching apparatus selects the task management block assigned to the time slot and executes the task.

Task switching apparatus, method and program

The inter-module communication apparatus includes a first module and a second module which operate individually on a processor; a common memory interposed between the first module and the second module for functioning as a communication medium; a plurality of communication paths provided to the common memory for connecting the first module and the second module to be communicable; a transmission unit for transmitting communication data from the first module to the second module; a reception unit for receiving the communication data transmitted from the first module by the second module; a processing order relating device for registering a processing order of communication processing, which is set between each communication path constituting a plurality of the communication paths; and a processing order relevance register which, for transmission, registers the processing order to the processing order relating device when the processing order is set for the communication data to be transmitted.

Inter-module communication apparatus

Provided is a program execution apparatus that appropriately determines an execution sequence of tasks each given a target completion time before which execution of the task is to be completed, and executes the tasks according to the determined execution sequence. For each task a plurality of types of priorities having a hierarchical relationship among them are set. The apparatus includes: a storing unit that stores an identifier of each task that is already in existence, at a memory position therein determined based upon a plurality of types of priorities set for each task; a receiving unit that receives an identifier of a new task, and a plurality of types of priorities set for the new task; and a writing unit that writes the received identifier at a memory position in the storing unit determined based upon the received plurality of types of priorities.

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Osaka, Japan

Kunihiko Hayashi