Fujitsu Corporation

Semiconductor Technology Academic Research Center

Fujitsu Vlsi Limited

Fugitsu Limited

Kunihiko Gotoh

Yuji Segawa

Osamu Kobayashi

Hiroyuki Nakamoto

Atsushi Iwata

Makoto Koga

Takeshi Yoshida

Mitsuya Kawata

Kunimitsu Kousaka

Kenichi Matsumaru

Kazuhiro Kitani

Hiroshi Yamazaki

Daisuke Yamazaki

Masahiro Kudo

Atsushi Matsuda

Hirokazu Tanaka

Tachio Yuasa

Toshiharu Takaramoto

Yoshihiro Masui

Yukinori Abe

Kazuaki Oishi

Masato Yoshioka

Kimitoshi Niratsuka

Akihiko Ito

Hajime Kurata

Yoshiaki Shimizu

Takahiro Watai

Mamoru Sasaki

Yoshihisa Takayama

Takeshi Yamamura

Tetsuji Funaki

Tadahiro Saito

Toru Mizutani

Yoshinori Yoshikawa

Takeshi Takayama

Tadayoshi Kunitoki

Kazuyoshi Fujita

Yuuji Sekido

Tetsuo Yagyu

Noboru Inanami

Masatake Kusakari

Katsuaki Aizawa

A folded cascode operational amplifier includes a constant current source to output a constant current; a differential input stage to output a part of the constant current as a differential current based on a voltage difference between voltages input to an inverting input terminal and a non-inverting input terminal, and connected to the constant current source; and an output stage to output a remaining current obtained by subtracting the differential current from the constant current as an output stage current, and connected parallel to the differential input stage facing the constant current source.

Operational amplifier, analog arithmetic circuit, and analog to digital converter

A switched capacitor circuit, which is operable in two or more kinds of operation modes including a first and second operation modes, includes an amplifier and two or more internal capacitors with switches for controlling connection/disconnection of the capacitor. In the first operation mode that precedes the second operation mode, the switched capacitor circuit generates the first analog output voltage by using the first internal capacitor connected between an input terminal and output terminal of the amplifier by using its switches, the other internal capacitances connected between an input terminal of the amplifier and each analog input voltage supply by using its switches. In the second operation mode, the switched capacitor circuit generates the second analog output voltage with larger feedback factor of the amplifier than it in the first operation mode, by removing some of the internal capacitors, except the first internal capacitor, from the first operation mode.

Switched capacitor circuit and stage circuit for AD converter

There is provided an analog-digital conversion cell being an analog-digital conversion cell that performs an N-bit analog-digital conversion (where N is a natural number) and including: a comparison circuit () comparing an analog input signal VI based on a plurality of reference voltages and outputting a first digital code DA selected from Q digital codes (where Q is a natural number equal to or more than 2+1 and equal to or less than 2&#x2212;1) in accordance with a size of the analog input signal VI; a first logic operation circuit () outputting a second digital code DB selected from Q digital codes, which is expressed by DB=DA&#xd7;KA+DBwhere a constant KA is a decimal number satisfying a condition of 1&#x3c;KA&#x3c;2 and DBis a constant, based on the first digital code DA; and an analog operation circuit () outputting an analog output signal VO expressed by VO=A&#xd7;(VI&#x2212;DA&#xd7;KA&#xd7;(VR/A)) where A and VR are constants, based on the first digital code DA and the analog input signal VI.

Analog-digital conversion cell and analog-digital converter

A differential amplifier circuit is provided with an operational amplifier and a modulator. The operational amplifier includes a feedback capacitance, and amplifies an analog input signal and outputs an amplified analog output signal. The modulator is connected to a virtual ground point of an input terminal of the operational amplifier, and the modulator switches between a pair of inputted analog differential signals to alternately select one of the analog differential signals based on a predetermined modulation control signal, and outputs a selected analog differential signal. The differential amplifier circuit alternately folds and amplifies the analog input signal within a predetermined input level limit range to generate a signal having different polarities sequentially so as to start from a voltage potential of the virtual ground point at a timing of the modulation control signal. In addition, an converter apparatus is provided with the differential amplifier circuit.

Differential amplifier circuit amplifying differential signals with selectively switching between differential signals and AD converter apparatus

There is provided a reference voltage generating circuit including: a first PN junction element (PN) whose forward voltage is a first voltage V; a second PN junction element (PN) having a current density different from the first PN junction element and whose forward voltage is a second voltage Vhigher than the first voltage V; and generating circuits (to) inputting the first voltage Vand the second voltage Vand generating a reference voltage expressed by A&#xd7;V+A&#xd7;(A&#xd7;V&#x2212;A&#xd7;V) in which A, A, and Aare set to be coefficients, and in which Aand Aare different values.

Reference voltage generating circuit

A modulation ratio enhancement circuit increases the modulation ratio of a current signal which is ASK-modulated with signal data. A branch unit, an average value detection unit, a comparator and a buffer constitute a demodulation unit so that the signal data is demodulated from a current signal of which the modulation ratio is increased by the modulation ratio enhancement circuit.

Demodulation circuit

Disclosed is a rectifier circuit that realizes a low threshold voltage without using a process step to enable reduction in cost and in variation of devices. An NMOS transistor has a threshold voltage. In the transistor, a voltage to be rectified is inputted to a second node, and a rectified voltage is outputted to a first node. A threshold voltage generator is connected to a gate of the transistor and the first node. The generator generates a voltage and outputs it to the gate of the transistor. The voltage is a voltage which is elevated by the threshold voltage with respect to a voltage of the first node and is decreased by a microvoltage sufficiently small with respect to the threshold voltage. Thus, when the voltage of the second node is decreased by the microvoltage or more with respect to that of the first node, the transistor is turned on.

Rectifier circuit

A reference voltage generator circuit is provided which is capable of stable generation of a reference voltage. A differential amplifier circuit has a non-inverting input terminal input with the voltage Vbegenerated by a PNP transistor Qand an inverting input terminal input with an output signal thereof. A differential amplifier circuit has a non-inverting input terminal input with the voltage Vbegenerated by a PNP transistor Qand an inverting input terminal input with the output signal of the differential amplifier circuit through a resistor Rand also input with an output signal thereof through a resistor R, to generate a reference voltage Vref.

Reference voltage generator circuit

In a feedback amplifier circuit, a first switching device executes an auto-zero operation by inputting a signal outputted from an amplifier to an input terminal of the amplifier during an auto-zero operation interval prior to an amplification interval. A first capacitor accumulates and holds an offset voltage at the output terminal of the amplifier during the auto-zero operation interval, and cancels an offset voltage at the input terminal of the amplifier by an accumulated and held offset voltage during an amplification interval subsequent to the auto-zero operation interval. A second switching device grounds the feedback point of the feedback circuit during the auto-zero operation interval. A second capacitor blocks a DC voltage, and accumulates and holds an offset voltage at an output terminal of the amplifier, and cancels an offset voltage at an input terminal of the amplifier by the accumulated and held offset voltage during an amplification interval.

Feedback amplifier circuit operable at low voltage by utilizing switched operational amplifier and chopper modulator

An encoder circuit and A/D converter that can minimize the error of an encoder output with respect to all the possible combinations of thermometer codes are desired to be provided. To this end, an encoder circuit has a logic thereof configured to take a thermometer code as an input and to output as an encoded value a center value of a range in which one or more encoded values are distributed, the one or more encoded values corresponding to positions of one or more boundaries between '0' and '1' appearing in the thermometer code.

Encoder circuit and A/D conversion circuit

In a class AB CMOS output circuit provided with a CMOS circuit including first P and N channel transistors and operating by a predetermined operating current I, a replica circuit is formed on a semiconductor substrate of the CMOS circuit, and includes a second P channel transistor having a size equal or similar to that of the first P channel transistor, and a second N channel transistor having a size equal or similar to that of the first N channel transistor. A bias voltage supply allows the second P and N channel transistors to operate based on a reference current Iref corresponding to the operating current I, applies a first bias voltage as applied to the second P channel transistor to the first P channel transistor, and applies a second bias voltage as applied to the second N channel transistor to the first N channel transistor.

Class AB CMOS output circuit equipped with CMOS circuit operating by predetermined operating current

A semiconductor integrated circuit includes a substrate, a digital circuit formed on a triple well formed in the substrate, a first node configured to supply a well potential of the digital circuit, a second node separate from the first node, and a substrate-potential supplying circuit, formed on the substrate, having an input node to receive an input potential from the second node and an output node to supply a substrate potential to the substrate, the substrate-potential supplying circuit having no direct-current path into which a direct current substantially flows through the input node, and configured to generate at the output node an output potential following the input potential.

Semiconductor integrated circuit with noise reduction circuit

A common-mode feedback circuit outputs a control voltage to define a common-mode operating point of a fully differential amplifier. The common-mode feedback circuit has a voltage dividing circuit and a differential amplifier. The voltage dividing circuit divides a voltage across two output ends of the fully differential amplifier. The differential amplifier receives an output voltage of the voltage dividing circuit and a reference voltage, and an output voltage of the differential amplifier is supplied as the control voltage to the fully differential amplifier.

Common-mode feedback circuit and differential operational amplifier circuit having stable operation and low power consumption

A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.

Semiconductor device and method for testing semiconductor device

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Kawasaki, Japan

Kunihiko Gotoh