International Business Machines Corporation

Kyocera Corporation

Adeia Semiconductor Bonding Technologies Inc.

Chi Mei Optoelectronics Corporation

Kuniaki Sueoka

Akihiro Horibe

Yoichi Taira

Toyohiro Aoki

Sayuri Hada

Eiji Nakamura

Takashi Hisada

Kazushige Toriyama

Chitra K Subramanian

Seiji Munetoh

Hiroyuki Mori

Hidetoshi Numata

Yasuteru Kohda

Shigeru Nakagawa

Yasumitsu K Orii

Takahito Watanabe

Hiroshi Suzuki

John Ulrich Knickerbocker

Paul Stephen Andry

Lubomyr Taras Romankiw

Katsuyuki Sakuma

Keiji Matsumoto

Takatoshi Tsujimura

Fuminori Sai

Toru Aihara

Mitsuo Morooka

Koichi Miwa

Hajime Nakamura

Risa Miyazawa

Sayuri Kohara

Osaaki Watanuki

Keizoh Takeda

Yohichi Taira

A technique relating to a battery structure is disclosed. A base substrate and a battery layer having a support substrate are prepared. The battery layer includes a protection layer formed on the support substrate, a film battery element formed on the protection layer and an insulator covering the film battery element. The battery layer is placed onto the base substrate with the bottom of the support substrate facing up. The support substrate is then removed from the battery layer at least in part by etching while protecting the film battery element by the protection layer. A stacked battery structure including the base substrate and the two or more battery layers is also disclosed.

Large capacity solid state battery

A device for applying underfill material into a space between a substrate and a semiconductor chip is provided. The device includes a frame housing configured to cover at least an outer edge area of the semiconductor chip that is bonded to the substrate. The device also includes a sealant attached to the frame housing and configured to contact the outer edge area of the semiconductor chip. The device also includes an outlet made on the frame housing for evacuating the space; and an inlet made on the frame housing for injecting the underfill material to the space.

Underfill injection for electronic devices

A method for sampling breath gas, includes collecting a first breath sample in a first bag. The first breath sample is an initial part of expired gas expired after inspiration. Additionally, the method includes collecting a second breath sample in a second bag. The second breath sample is a latter part of the expired gas. The method includes subtracting first mass spectral data obtained by mass spectroscopy of the first breath sample collected in the first bag from second mass spectral data obtained by mass spectroscopy of the second breath sample collected in the second bag.

Sampling of breath gas

A method for fabricating a stacked device structure includes preparing plural device layers each having a glass layer, a metal layer, and a resin layer. The metal layer corresponds to one of plural metal layers. The method further includes stacking the plural device layers to compose stacked device layers; and drilling vertically a hole into the stacked device layers by laser such that the plural metal layers are exposed to the hole and filling conductive material into the hole to connect the plural metal layers.

Stacked device structure

A method for fabricating a stacked battery structure. The method includes preparing a plurality of battery layers separately, wherein each battery layer includes a substrate, a film battery element fabricated on the substrate and an insulator formed over the film battery element. The insulator has a flat top surface and the film battery element includes a current collector. The method also includes stacking the plurality of battery layers, wherein the insulator of a first battery layer of the plurality of battery layers bonds to the substrate of a second battery layer of the plurality of battery layers by the flat top surface. The method further includes forming a conductive path within the plurality of battery layers, wherein the conductive path connects with at least one of the current collectors of the plurality of battery layers.

Stacked film battery architecture

A method for fabricating an electron device stack structure includes preparing plural substrates, each having a corresponding one of plural vias; sputter-depositing plural metal layers on the plural substrates to form plural electron device layers, each of the plural metal layers being sputter-deposited on a corresponding one of the plural substrates and including a part straying into a corresponding one of the plural vias as a corresponding one of plural stray metal portions; stacking the plural electron device layers to construct the electron device stack structure having a conductive path formed by connecting the plural vias; and injecting a conductive material into the conductive path to form a vertical electrical connection among the plural stray metal portions.

Electron device stack structure

There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module includes a circuit board provided with a plurality of electrode pads on a surface of the board, a semiconductor chip arranged on the board, the chip including a surface and a back surface, where each of a plurality of solder bumps and provided on the back surface is solder joined to a corresponding one of the plurality of electrode pads, and an underfill provided between the surface of the board and the back surface of the chip. Furthermore, the chip includes an eaves portion of a predetermined thickness at an outer periphery of the surface, and the underfill forms a fillet extending from a bottom surface of the eaves portion to the surface of the board along a side wall of the chip.

Circuit module and manufacturing method thereof

A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.

Wafer scale testing and initialization of small die chips

A chip pickup system is provided. The chip pickup system includes a detector for detecting a position of an irregular semiconductor chip on a holder. The holder holding plural semiconductor chips in predetermined positions on the holder. The irregular semiconductor chip is out of the predetermined positions. The system further includes a pickup tool for picking up the irregular semiconductor chip at least on the basis of information on the position of the irregular semiconductor chip detected by the detector.

Picking up irregular semiconductor chips

Methods for depositing material on a chip include forming a mold layer. The mold layer includes one or more openings over respective contact areas, each of the one or more openings having an upper volume and a lower volume. The upper volume has a smaller diameter than a diameter of the lower volume. Each contact area is within the respective lower volume. A material is injected into the one or more openings under pressure.

Injection molded solder bumping

A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.

Reduction of stress in via structure

A method for filling a through hole with solder includes mounting a substrate having a through hole formed therein on a permeable barrier layer having pores that enable gas to flow through the permeable barrier. A solder source is positioned over the through hole. Molten solder is delivered in the through hole with a positive pressure from the solder source such that gas in the through holes passes the permeable barrier while the molten solder remains in the through hole.

Solder fill into high aspect through holes

Growing community of inventors

Kanagawa-ken, Japan

Kuniaki Sueoka