Vanguard International Semiconductor Corporation

Kung Linliu

Erik S Jeng

Tzu-shih Yen

Hsu-Li Cheng

Eric S Jeng

A method is disclosed for forming Y-shaped holes in semiconductor substrates by using Y-contact etching. The hole is formed with a single, two-step dry-etching process in a single chamber with one masking step for the whole hole. The upper portion of the Y-shaped hole is formed by means of an isotropic tapered dry-etching process while the lower portion is formed by means of a straight anisotropic recipe of the same dry-etching process. The result is a Y-shaped hole formed with fewer process steps and with maximized contact area for improved reliability.

Contact process using Y-contact etching

A method for forming a patterned polysilicon layer employed within an integrated circuit structure. There is first provided a semiconductor substrate having formed thereupon a topographic substrate layer. There is then formed over the semiconductor substrate including the topographic substrate layer a polysilicon layer. There is then formed over the polysilicon layer an etch mask layer. There is then etched the polysilicon layer within a first reactive ion etch (RIE) plasma employing a first etchant gas composition which comprises a chlorine containing etchant species to form a patterned polysilicon layer and a patterned polysilicon containing layer residue. Finally, there is then over-etched the patterned polysilicon layer and the patterned polysilicon containing layer residue within a second reactive ion etch (RIE) plasma employing a second etchant gas composition which comprises an oxygen containing etchant species and a bromine containing etchant species. The patterned polysilicon layer is formed while etching the patterned polysilicon containing layer residue from over the topographic substrate layer.

Method for forming residue free patterned polysilicon layer containing

A new method for forming a feature having a feature size of one half the resolution of the photolithography process by adjusting the etching conditions is achieved. A capping oxide layer is deposited overlying the feature layer. A first layer of photoresist is patterned using a photolithography process to provide a first photomask having a first feature size. The oxide layer is etched vertically through no more than half of its thickness and the photomask and oxide layer are etched horizontally to provide a first oxide mask having a second feature size one half the width of the first feature size. The first photomask is removed. A second photoresist layer is patterned to provide a second photomask for forming the second feature wherein the second photomask has a first feature size and is shifted horizontally by twice the desired feature size from the first photomask. The oxide layer is etched vertically through no more than half of its thickness and the photomask and oxide layer are etched horizontally to provide a second oxide mask having a second feature size one half the width of the first feature size. All of the capping oxide layer is removed except for the first and second oxide masks. The second photomask is removed. The feature layer is etched through where it is not covered by the first and second oxide masks to form the first and second features having the second line width of one half the resolution of the photolithography process in the manufacture of an integrated circuit device.

Method of forming a narrow polysilicon gate with i-line lithography

Voids in via holes in integrated circuits have been effectively removed by heating the vias to a relatively low temperature and then subjecting the entire structure (including the vias) to artificial gravitational forces. Said forces may be steadily applied, as in centrifuging, or they may be applied intermittently by using a jerking motion which is repeated several times. A number of different ways for implementing such jerking motion are described. These include magnetic repulsion, vertical pulling by a motor, and providing a pressure differential between the top and bottom sides of the integrated circuit holder.

Metallization process using artificial gravity

The time needed to planarize the surface of an integrated circuit is reduced by causing the planarization liquid to settle in the presence of artificial gravity that supplements natural gravity. A number of different ways to achieve artificial gravity are described. These include centrifuging, magnetic repulsion, vertical pulling by a motor, and providing a pressure differential between the top and bottom sides of the wafer holder.

Planarization process using artificial gravity

A method for forming a patterned layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket target layer. There is then formed upon the blanket target layer a blanket focusing layer formed from an organic anti-reflective coating (ARC) material, where the blanket focusing layer is susceptible to a reproducible negative etch bias within a first etch method employed in forming from the blanket focusing layer a patterned focusing layer. The first etch method is a first plasma etch method employing a reactant gas composition comprising trifluoromethane, carbon tetrafluoride, oxygen and argon. There is then formed upon the blanket focusing layer a blanket photoresist layer which is photoexposed and developed to form a patterned photoresist layer. There is then etched through the first etch method the blanket focusing layer to form the patterned focusing layer while employing the patterned photoresist layer as a first etch mask layer, where the patterned focusing layer has the reproducible negative etch bias with respect to the patterned photoresist layer. Finally, there is etched through a second etch method the blanket target layer to form a patterned target layer while employing the patterned focusing layer as a second etch mask layer. The patterned target layer has a reproducible second etch bias with respect to the patterned focusing layer, where the reproducible second etch bias does not substantially compensate the reproducible negative etch bias. Through the method, there may be formed patterned layers, such as gate electrodes within field effect transistors (FETs), of linewidth at least as narrow as about 0.25 micron while employing near ultra-violet (NUV) (ie: 365 nm) photoexposure radiation.

Method for controlling linewidth by etching bottom anti-reflective

A method for manufacturing an array of double-crown-shaped storage capacitors with increased capacitance on a dynamic random access memory (DRAM) device has been achieved. The invention utilizes a polysilicon and silicon nitride spacer to form the double-crown capacitors while forming concurrently bit lines and node contacts for the bottom electrodes of the storage capacitors. A silicon nitride layer and a silicon nitride spacer are used to insulate the bit lines from the capacitors formed thereon. The polysilicon sidewall spacer is used to pattern a very narrow vertical insulating structure on which is formed the polysilicon double crown by depositing another polysilicon layer which is etched back. The vertical insulating structures are removed by selective etching leaving a free-standing bottom electrode having a double-crown-shaped structure. An interelectrode dielectric layer having a high dielectric constant, and a final polysilicon layer are deposited to complete the storage capacitors for the DRAM.

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Kung Linliu