Xilinx, Inc.

Sandisk Technologies Inc.

Kunal Ramachandra Shenoy

Ahmad R Ansari

Jeffery H Appelbaum

Oded Karni

Kevin Leigh Goodwin

Nolen Velasco

Saranyan Rajagopalan

Jeffery H Applebaum

Techniques described herein relate to updating firmware of multiple non-volatile memory devices having diverse configurations using a common update file. The non-volatile memory device may include a flash memory device having a non-volatile memory array. Particular implementations described herein relate to circuits, devices, systems, and methods that update, with a common update file, firmware residing on multiple non-volatile memory devices having diverse configurations.

Firmware updates for multiple product configurations

A crossbar switch device for a processor block ASIC core and a method for a flush-posted-write(s)-before-read mode thereof are described. Operation for the flush-posted-write(s)-before-read mode is set in a first processor block interface coupled to programmable logic fabric. At least one write command is sent from a transaction initiating device instantiated using the programmable logic fabric to the first processor block interface. The at least one write command is posted in the first processor block interface. At least one write command received is stored in a command queue of the crossbar switch device. A read command initiated by a microprocessor is sent to the crossbar switch device. The at least one write command has an address overlap with the read command with respect to a destination target. The read command is temporarily blocked in the crossbar switch device until a command phase of the at least one write command is completed.

Crossbar switch device for a processor block core

Arbitration for a processor block core is described. Master devices are associated with a processor block core embedded in a host integrated circuit ('IC'). The master devices are coupled to core logic of the host IC via a crossbar switch and a bridge, which are part of the processor block core. The crossbar switch includes an arbiter. An arbitration protocol is selected from among a plurality of arbitration protocols for use by the arbiter. Pending transactions having are polled for access to the bridge for arbitration using the arbitration protocol selected.

Arbitration for an embedded processor block core in an integrated circuit

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San Jose, CA, United States of America

Kunal Ramachandra Shenoy