Micron Technology Incorporated

Aptina Imaging Corporation

Lodestar Licensing Group LLC

Other

Micro Technology, Inc.

Kunal R Parekh

John K Zahurak

Kyle K Kirby

Li Li

Justin B Dorhout

Martin Ceredig Roberts

Mark Fischer

Zhiqiang (Jeff) Wu

Gurtej S Sandhu

Charles H Dennison

Chet E Carter

Phillip G Wald

David A Daycock

Jun Liu

Richard H Lane

H Montgomery Manning

Vinayak Shamanna

Ryan L Meyer

Thomas Arthur Figura

Paolo Tessariol

Mohd Kamran Akhtar

Mark E Jost

Suraj J Mathew

Matthew Park

David L Dickerson

Sarah A Niroumand

Glen Earl Hush

Alan R Reinberg

Sean Stephen Eilert

Jigish D Trivedi

Pai-Hung Pan

Kunal Shrotri

David K Hwang

Aliasger Tayeb Zaidy

Kin F Ma

Cem Basceri

Thomas M Graettinger

Yushi Hu

Joseph Neil Greeley

Angela S Parekh

Chandra V Mouli

John David Hopkins

Akira Goda

Aaron S Yip

Fatma Arzum Simsek-Ege

Bret K Street

William Arthur Stanton

Fei Wang

Jeffrey W Honeycutt

Byron Neville Burgess

Fawad Ahmed

Wei Zhou

Ian C Laboriante

Sanh D Tang

Haitao Liu

Pierre C Fazan

Zhiping Yin

Philip J Ireland

Indra V Chary

Nancy M Lomeli

David S Becker

Paul J Schuele

Thomas R Glass

Jasper S Gibbons

Michael J Hermes

Brent Keeth

Fernando N Gonzalez

Werner Juengling

John A Smythe

Randhir P S Thakur

Nishant Sinha

Chris M Carlson

Bhaskar Srinivasan

James Brian Johnson

Hongbin Zhu

Anish A Khandekar

Eiichi Nakano

Steven M McDonald

Dimitrios Pavlopoulos

Beau D Barry

M Jared Barclay

Merri Lyn Carlson

Zhiqiang Xie

Amy R Griffin

Saurabh Keshav

Darren V Young

Randhir P Thakur

Vishnu Kumar Agarwal

George Matamis

F Daniel Gealy

Ceredig Roberts

Terrence B McDaniel

Young Pil Kim

M Ceredig Roberts

Akshay N Singh

Steve V Cole

Bharat Bhushan

Thy Tran

Surendranath C Eruvuru

A microelectronic device comprises a stack structure, cell pillar structures, an active body structure, digit line structures, and control logic devices. The stack structure comprises vertically neighboring tiers, each of the vertically neighboring tiers comprising a conductive structure and an insulative structure vertically neighboring the conductive structure. The cell pillar structures vertically extend through the stack structure and each comprise a channel material and an outer material stack horizontally interposed between the channel material and the stack structure. The active body structure vertically overlies the stack structure and is in contact with the channel material of the cell pillar structures. The active body structure comprises a metal material having a work function greater than or equal to about 4.7 electronvolts. The digit line structures vertically underlie the stack structure and are coupled to the cell pillar structures. Memory devices, electronic systems, and methods of forming a microelectronic device are also described.

Microelectronic devices, memory devices, and 3D NAND flash memory devices

A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a preliminary stack structure comprising sacrificial structures and insulative structures vertically alternating with the sacrificial structures. A second microelectronic device structure comprising control logic circuitry is formed. The first microelectronic device structure is attached to the second microelectronic device structure to form an assembly. After forming the assembly, the sacrificial structures are at least partially replaced with conductive structures to form a stack structure. Contact structures are formed to extend through the stack structure. One or more of the contact structures are coupled to the control logic circuitry. Conductive line structures are formed over the stack structure. One or more of the conductive line structures are coupled to the one or more of the contact structures. Microelectronic devices, memory devices, and electronic systems are also described.

Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems

Methods, systems, and devices for repair techniques for coupled host and memory dies are described. For example, to distribute memory access circuitry among multiple semiconductor dies of a stack, a first die may include a set of one or more memory arrays and a first portion of circuitry configured to access the set of memory arrays, and a second die may include a second portion of circuitry configured to access the set of memory arrays. The second portion of the circuitry (e.g., of the second die) may be configured to support various repair techniques for operations with the set of memory arrays, including techniques in response to column failures or serialization failures associated with the first die, or in response to contact or other interconnection failures with or between the first die and the second die, among other techniques that may be differentiated based on an attribution of error conditions.

Repair techniques for coupled memory dies

A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material sintering therein.

Monolithic conductive column in a semiconductor device and associated methods

A semiconductor device having monolithic conductive cylinders, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, and a top dielectric layer. The conductive pad may be at a first surface of the semiconductor substrate. The opening may be ring-shaped and extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the top dielectric layer may cover the second surface and may fill the opening. A second ring-shaped opening may be formed through the semiconductor device and the opening and a conductive material plated therein.

Monolithic conductive cylinder in a semiconductor device and associated methods

A semiconductor device assembly can include an assembly substrate having a top surface, a top semiconductor device having a bottom surface, and a plurality of intermediary semiconductor devices. Each of intermediary semiconductor device can be bonded to both the assembly substrate top surface and the top device bottom surface. Each intermediary semiconductor device can also include a semiconductor substrate, a memory array, a first bond pad, a second bond pad, and a conductive column. The first bond pad can electrically couple the assembly substrate to the intermediary semiconductor device; the second bond pad can electrically couple the top semiconductor device to the intermediary semiconductor device; and the conductive column can electrically couple the first bond pad to the second bond pad, and can be exclusive of any electrical connection to the memory array.

Semiconductor device assemblies and associated methods

A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. Memory devices can be formed on a first wafer. First metal pads can be formed on the first wafer and coupled to the memory devices. The memory devices can be tested via the first metal pads. The first metal pads can be removed from the first wafer. Subsequently, second metal pads on the first wafer can be bonded, via a wafer-on-wafer bonding process, to third metal pads on a second wafer. Each memory device on the first wafer can be aligned with and coupled to a respective logic device on the second wafer.

Testing memory of wafer-on-wafer bonded memory and logic

Systems and methods for a semiconductor device having a front-end-of-line structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor substrate material and a front side, and an interconnect structure extending through the dielectric material. The interconnect structure may be electrically connected to a semiconductor memory array proximate the front side of the dielectric material. The semiconductor device may further have an insulating material encasing at least a portion of the semiconductor memory array and an opening created during back-end-of-line processing through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.

Front end of line interconnect structures and associated systems and methods

Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

Microelectronic devices with through-substrate interconnects and associated methods of manufacturing

Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies and methods of forming integrated assemblies

A semiconductor device assembly includes a first semiconductor device having front and rear surfaces, a plurality of front-side pads disposed over the front surface at a first distance from the rear surface, and a plurality of additional device pads disposed over the front surface at a second distance from the rear surface greater than the first distance; a second semiconductor device in contact with a top side of each of the additional device pads; an encapsulant material at least partially surrounding the second semiconductor device and covering a top side of the front-side pads; a first plurality of TSVs, each extending from the rear surface through the first semiconductor device to a bottom side of one of the front-side pads; and a second plurality of TSVs, each extending from the rear surface through the first semiconductor device to a bottom side of corresponding one of the additional device pads.

Semiconductor device assemblies including TSVs of different lengths and methods of making the same

A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data.

Signal routing between memory die and logic die for performing operations

Systems and methods for a semiconductor device having a front-end-of-line interconnect structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor or silicon substrate material and a front side, and a conducting material on the front side of the dielectric material. The conducting material may have a line portion and an interconnect structure electrically coupled to the line portion and separated from the front side of the substrate material by the dielectric material. The interconnect structure has a backside defining a contact surface. The semiconductor device may further include a semiconductor die proximate the front side of the dielectric material, an insulating material encasing at least a portion of the semiconductor die, and an opening through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.

Memory devices and related methods of forming a memory device

Methods, systems, and devices for memory with parallel main and test interfaces are described. A memory die may be configured with parallel interfaces that may individually (e.g., separately) support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack). For example, a memory die may include a first set of one or more contacts that support communicating signaling with or via another memory die in a multiple-die stack. The memory die may also include a second set of one or more contacts that support probing for pre-assembly evaluations, which may be electrically isolated from the first set of contacts. By implementing such parallel interfaces, evaluation operations may be performed using the second set of contacts without damaging the first set of contacts, which may improve capabilities for supporting a multiple-die stack in a memory device.

Memory with parallel main and test interfaces

Growing community of inventors

Boise, ID, United States of America

Kunal R Parekh