Microsoft Technology Licensing, LLC

Kunal Pathak

Dinesh Chandnani

Ritesh Rambhai Parikh

Andrew Edward Ayers

Compilation is supported and improved by varying the order of invocation of register allocation heuristics during code generation. A particular invocation order may be chosen based on one or more compilation scenario properties, such as a target processor architecture, a target operating system, a kind of source code being compiled, or optimization targets for the compiler or the generated code, or a mix thereof. Suitable heuristics invocation orders may be produced efficiently and effectively using a genetic algorithm that is adapted to make a population of invocation orders, select parents, create offspring, and assess invocation order fitness, until the population converges on optimal orders. Invocation order fitness assessments may be based on actual performance or simulated performance.

Register allocation heuristics order

Debugging and testing are aided by removing portions of software which are not relevant to a particular scenario. Upon replay, scenario behavior occurs. A reduction tool selects a function exercised during the replay, disables it to provide a test version of the software, replays the scenario to the test version to produce a candidate behavior, and compares the candidate behavior to the scenario behavior. When the candidate behavior matches the scenario behavior the tool removes the disabled function, thereby providing a reduced version of the software which is functionally equivalent to the full version but has fewer functions to manage. The tool may also remove unexercised code. Trimming unexercised code and reducing exercised but irrelevant code may be interleaved. Caching, dynamic uniform resource locator mapping, hypertext markup language code refactoring, and/or avoidance of certain random elements may also facilitate exhibiting, testing, or debugging web applications.

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Redmond, WA, United States of America

Kunal Pathak