Qualcomm Incorporated

Kunal Mukesh Desai

Umesh Madhusudan Rao

Dharmesh Parikh

Satyaki Mukherjee

Vikrant Kumar

Pranav Agrawal

Vinayak Shrivastava

Saurabh Jaiswal

Abhinav Mittal

Siddharth Kamdar

Deepak Kumar Agarwal

Piyush Gupta

Srinivas Maddali

Kiran Kumar Malipeddi

Swaraj Sha

Bernie Jord Yang

Vasantha Kumar Bandur Puttappa

Ankit Shambhu

Sanjeev Shukla

Jimit Shah

Rakesh Gehalot

Akash Suthar

Aman Chhetry

Shekar Babu Merla

A die-to-die serial data link may be dynamically configured to exclude lanes associated with data errors. In a test mode, data may be transmitted from a first die to a second die over lanes of the link. In the second die, data received on the link in the test mode may be compared with an expected data pattern to detect any bit mismatches. When there are no more than a threshold number of mismatched bits, a receive path in the second die may be configured to use all of the lanes. When there are more than the threshold number of mismatched bits, a sub-group of the lanes that are not associated with mismatched bits may be determined, and the receive path in the second die may be configured to use the sub-group of lanes. In the first die, a transmit path may be configured to use the sub-group of lanes.

Dynamic die-to-die serial lane configuration

A kernel of an HLOS may originate one or more memory refresh requests. Each memory refresh request may have a first memory address range and a size value. A resource power manager may be coupled to the kernel and coupled to memory. The memory may have a plurality of memory ranks. The resource power manger may receive a memory refresh request from the kernel. The resource power manager may then determine if the plurality of memory ranks is either symmetrical or asymmetrical. If the memory ranks are symmetrical, then the resource power manager distributes the memory refresh request evenly and in a parallel manner across the symmetrical memory ranks. If the memory ranks are asymmetrical, then the resource power manager will then determine if the memory refresh request should be one of: a linear only memory refresh; an interleave with linear memory refresh; or an interleave only memory refresh.

Method and system for refreshing memory of a portable computing device

Various embodiments include methods and devices for portion interleaving for asymmetric size memory portions. Embodiments may include determining an asymmetric memory portion assignment for an interleave unit, determining a consumed address space offset for consumed address space of a memory, modifying an address of the interleave unit using the consumed address space offset, and assigning the interleave unit to an interleave granule in the asymmetric memory portion using the modified address in a compact manner before assigning another interleave unit to another interleave granule. Embodiments may include receiving an address of memory access request in a memory, mapping the address to an interleave granule in an asymmetric memory portion, assigning consecutive interleave units to the interleave granule while the interleave granule has unused space before assigning another interleave unit to another interleave granule, and implementing the memory access request at the mapped address.

Effective DRAM interleaving for asymmetric size channels or ranks while supporting improved partial array self-refresh

Various embodiments may include methods and systems for reconfiguring memory channel routing within a system-on-a-chip (SoC). A method may include obtaining first error information in response to misbehavior in a first memory channel communicatively connected to a network interface unit (NIU) of the SoC. The method may further include storing the first error information in non-volatile memory that is read upon booting of the SoC, and rebooting the SoC including the first memory channel. The method may further include configuring the first memory channel to be communicatively disconnected from the NIU and configuring a second memory channel to be communicatively connected to the NIU in response to reading the stored first error information during reboot.

Devices and methods for safe mode of operation in event of memory channel misbehavior

Error detection and correction (EDAC) logic of a memory subsystem may be monitored for error corrections, with the EDAC logic configured to use a first EDAC level. The number of error corrections made by the EDAC logic while using the first EDAC level during a time interval may be determined. The EDAC logic may be switched from using the first EDAC level to using a second EDAC level when the number of error corrections using the first EDAC level during the time interval exceeds a threshold.

Adaptive memory error detection and correction

A system-on-a-chip ('SoC') in a computing device may be provided with a power delivery network ('PDN') self-test to detect marginal PDN performance. In the self-test, a current surge may be generated on power supply connections of logic circuit blocks. Voltage monitors may measure voltage droop on the power supply connections responsive to the current surge. Voltage droop measurements may be compared with thresholds. An action, such as generation of an alert, may be performed if a voltage droop measurement exceeds a threshold.

Detecting power delivery network marginality in a computing device

Systems, methods, and computer programs are disclosed for managing memory channel connectivity. One embodiment of a system comprises a high-bandwidth memory client, a low-bandwidth memory client, and an address translator. The high-bandwidth memory client is electrically coupled to each of a plurality of memory channels via an interconnect. The low-bandwidth memory client is electrically coupled to only a portion of the plurality of memory channels via the interconnect. The address translator is in communication with the high-bandwidth memory client and configured to perform physical address manipulation when a memory page to be accessed by the high-bandwidth memory client is shared with the low-bandwidth memory client.

Bandwidth-based selective memory channel connectivity on a system on chip

Methods and systems for dynamically controlling buffer size in a computing device in a computing device ('PCD') are disclosed. A monitor module determines a first use case for defining a first activity level for a plurality of components of the PCD. Based on the first use case, a plurality of buffers are set to a first buffer size. Each of the buffers is associated with one of the plurality of components, and the first buffer size for each buffer is based on the first activity level of the associated component. A second use case for the PCD, different from the first use case, is determined. The second use case defines a second activity level for the plurality of components. At least one of the buffers is set to a second buffer size different from the first buffer size based on the second use case.

System and method for dynamic buffer sizing in a computing device

Systems, methods, and computer programs are disclosed for dynamically adjusting memory channel interleave granularity. An embodiment of a system comprises a plurality of memory clients, a memory management unit (MMU), and an address translator. The plurality of memory clients are electrically coupled to each of a plurality of memory channels via an interconnect. The MMU is configured to receive a request for a memory allocation request for one or more memory pages from one of the plurality of memory client and, in response, select one of a plurality of interleave granularities for the one or more memory pages. The address translator is configured to translate a physical address to interleave memory data associated with the one or more memory pages at the selected interleave granularity.

Dynamic adjustment of memory channel interleave granularity

A configurable die including a logic element configured to communicate a control and address (CA) signal and a data (DQ) signal, and a first generic physical interface (PHY) and a second generic PHY in communication with the logic element, wherein each of the first generic PHY and the second generic PHY is configurable as a CA PHY and as a DQ PHY, and wherein the logic element is configurable to communicate the CA signal and the DQ signal to different ones of the first and second generic PHYs.

Growing community of inventors

Bengaluru, India

Kunal Mukesh Desai