Rambus Inc.

Xilinx, Inc.

Silicon Image Gmbh

Kun-Yung Chang

Yohan Usthavia Frans

Abhijit Mukun Abhyankar

Ting Wu

Scott C Best

Frank Lambrecht

Geoffrey Zhang

Yu Xu

Parag Upadhyaya

Chintan S Thakkar

Fariborz Assaderaghi

Hongtao Zhang

Zhaoyin D Wu

Hae-Chang Lee

Yu Liao

Kee Hian Tan

Jafar Savoj

Farshid Aryanfar

Mayank Raj

Alan C Wong

Winson Lin

Christopher J Borrelli

Siok Wei Lim

Caleb S Leung

Mark A Horowitz

Kevin S Donnelly

Austin H Lesea

Stefanos Sidiropoulos

Carl William Werner

Cheng-Hsiang Hsieh

Yingxuan Li

Kambiz Kaviani

Chaofeng Huang

Didem Z Turker Melek

Toan Duc Pham

Kok Lim Chan

Masoud Koochakzadeh

Sen Lin

Chin Yang Koay

Hongyuan Zhao

Brian S Leibowitz

Amir Amirkhany

Suresh Ramalingam

Donald Victor Perino

Nhat M Nguyen

Elad Alon

Jason C Wei

Jie Shen

Wayne D Dettloff

Sudhakar Pamarti

Chuan Xie

Xudong Shi

Wayne Fang

Yipeng Wang

Nakul Narang

Santiago G Asuncion

Ping-Chuan Chiang

Arianne Roldan

Tianqi Tang

Jun-Chau Chien

A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.

Drift tracking feedback for communication channels

An improved chip package, and methods for fabricating the same are provided that utilize two tier packaging of an optical die and another die commonly disposed over a substrate. In one example, a chip package is provided that includes an optical die, a core die, and an electrical/optical interface die are all disposed over a common substrate. In one example, a first routing region is provided between the core and electrical/optical interface dies, a second routing region is provided between the electrical/optical interface die and the optical dies, and a third routing region is disposed between the substrate and the core and electrical/optical interface dies.

Integrated electrical/optical interface with two-tiered packaging

A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO), a first loop circuit, and a second loop circuit. The first loop circuit includes a first loop filter configured to receive a first signal based on a feedback signal from the VCO and provide a first VCO frequency control signal to the VCO. The second loop circuit includes a compensation circuit configured to receive a reference signal and the first signal, and provide a second VCO frequency control signal to the VCO.

Method and apparatus for a phase locked loop circuit

Apparatus and associated methods relate to a high-speed data serializer with a clock calibration module including a main multiplexer (MMUX), a replicated multiplexer (RMUX), a duty cycle calibration module (DCC), and a set of adjustable delay lines (ADLs), the ADLs generating calibrated clocks from a set of system clocks, the DCC sensing duty cycle and phase of the calibrated clocks. In an illustrative example, the DCC may generate error signals indicative of deviation from an expected duty cycle using low-pass filters. The error signals control the ADLs, which may provide continuous corrections to the calibrated clocks, for example. The MMUX and RMUX may receive the calibrated clocks, the RMUX generating a duty cycle indicating clock-to-data phasing, the MMUX providing live data multiplexing, for example. Various multiplexer calibration schemes may reduce jitter, which may facilitate increased data rates associated with high-speed serial data streams.

Clock phase aligner for high speed data serializers

Examples herein describe techniques for isolating portions of an IC that include sensitive components (e.g., inductors or capacitors) from return current in a grounding plane. An output current generated by a transmitter or driver in an IC can generate a magnetic field which induces return current in the grounding plane. If the return current is proximate the sensitive components, the return current can inject noise which can negatively impact other components in the IC. To isolate the sensitive components from the return current, embodiments herein include forming slots through the grounding structure which includes the grounding plane on one or more sides of the sensitive components.

Isolation enhancement with on-die slot-line on power/ground grid structure

An example apparatus includes an input circuit including a first adder and a first multiplier, the first adder configured to level-shift an input signal by an amount and the first multiplier configured to multiply output of the adder by a factor. The apparatus further includes a multi-stage noise shaping (MASH) circuit having an input coupled to the first multiplier. The apparatus further includes an output circuit including a second multiplier and a second adder, the second multiplier configured to multiply output of the MASH circuit by a reciprocal of the factor and the second adder configured to level-shift output of the second multiplier by an inverse of the amount.

Delta-sigma modulator having expanded fractional input range

An example clock and data recovery (CDR) circuit includes a phase interpolator, a fractional-N phase locked loop (PLL) configured to supply a clock signal to the phase interpolator, and a phase detector configured to generate a phase detect result signal in response to phase detection of data samples and crossing samples of a received signal, the data samples and the crossing samples being generated based on a data phase and a crossing phase, respectively, or a sampling clock supplied by a phase interpolator. The CDR circuit further includes a digital loop filter configured to generate a phase interpolator code for controlling the phase interpolator, the digital loop filter including a phase path and a frequency path. The CDR circuit further includes a control circuit configured to control the digital loop filter to disconnect the frequency path from the phase path and to connect the frequency path to a control input of the fractional-N PLL.

Clock and data recovery circuit having tunable fractional-N phase locked loop

Systems and methods therefor relating generally to electro-absorption modulation are disclosed. In a system thereof, a waveguide is for propagating an optical signal. A segmented electro-absorption modulator ('SEAM') includes: a segmented anode having at least two anode segments spaced apart from one another alongside a first side of the waveguide; and a segmented cathode having at least two cathode segments spaced apart from one another alongside a second side of the waveguide corresponding to the at least two anode segments.

Segmented electro-absorption modulation

A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.

Impedance and swing control for voltage-mode driver

A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.

Apparatus and method for un-delayed decision feedback with sample and hold at selected timing

An example photodiode emulator circuit includes: a first current source circuit; first and second transistors having sources coupled together and coupled to an output of the first current source circuit, a drain of the second transistor coupled to a first node; a third transistor coupled between a drain of the first transistor and a replica load circuit; a second current source circuit coupled to the first node; a capacitor coupled between the first node and electrical ground; and a fourth transistor having a source coupled to the first node and a drain that supplies an output current.

Electrically testing an optical receiver

An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal; adjusting a phase of the sampling clock signal using a clock and data recovery (CDR) circuit based on the data samples and the crossing samples; adjusting relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees; and reverting the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.

Temporal change in data-crossing clock phase difference to resolve meta-stability in a clock and data recovery circuit

Systems, and related methods, relating generally to electro-absorption modulation are described. In a system therefor, there is a waveguide. A photodetector is configured with respect to the waveguide for detecting luminous intensity of an optical signal. An electro-absorption modulator is configured with respect to the waveguide for electro-absorption modulation of the optical signal. An integrated heating element is located alongside and spaced apart from both the photodetector and the electro-absorption modulator. the integrated heating element is configured for controllably heating the photodetector and the electro-absorption modulator.

Electro-absorption modulation with an integrated photodetector

Growing community of inventors

Los Altos, CA, United States of America

Kun-Yung Chang