Skhynix Inc.

Kun Young Lee

Tae Kyung Kim

Changhan Kim

Sung Hyun Yoon

Jae Gil Lee

Seo Hyun Kim

Sun Young Kim

Hyangkeun Yoo

Nam Kuk Kim

Dong Hyoub Kim

Embodiments of the present invention provide a hybrid memory and a hybrid memory manufacturing method including both a volatile memory and a nonvolatile memory on a single substrate so as to increase an operation speed of a semiconductor device and reduce manufacturing cost. A hybrid memory includes: a substrate; a non-volatile memory including an alternating stack in which a plurality of insulation layers and a plurality of horizontal word lines are alternately stacked on the substrate; and a volatile memory including a capacitor, the capacitor penetrating through the alternating stack.

Semiconductor device and method for fabricating the same

A method for fabricating a semiconductor device includes: forming a mold stack layer including a mold layer and a supporter layer over a substrate; forming opening by etching the mold stack layer; selectively forming a supporter reinforcement layer on an exposed surface of the supporter layer which is positioned in the opening; forming a bottom electrode in the opening in which the supporter reinforcement layer is formed; and forming a supporter opening by etching a portion of the supporter layer to form a supporter that supports an outer wall of the bottom electrode.

A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

Manufacturing method of a semiconductor memory device

A semiconductor device includes a stacked structure including conductive layers and gaps respectively interposed between the conductive layers, a channel layer passing through the stacked structure, a ferroelectric layer surrounding a sidewall of the channel layer, and first dielectric patterns interposed between the ferroelectric layer and the conductive layers, respectively. The gaps extending between the first dielectric patterns.

Semiconductor device and manufacturing method of the semiconductor device

A semiconductor device includes a stacked structure with conductive layers and insulating layers that are stacked alternately with each other, an insulating pillar passing through the stacked structure, a first channel pattern surrounding a sidewall of the insulating pillar, a second channel pattern surrounding the sidewall of the insulating pillar, a first insulator formed between the first channel pattern and the second channel pattern, and a memory layer surrounding the first channel pattern, the second channel pattern, and the first insulator, the memory layer with a first opening located that is between the first channel pattern and the second channel pattern.

Semiconductor device and manufacturing method of semiconductor device

A semiconductor device includes a stacked structure including conductive layers and insulating layers stacked alternately with each other, a channel layer passing through the stacked structure, a ferroelectric layer surrounding a sidewall of the channel layer, a first dielectric layer surrounding a sidewall of the ferroelectric layer, and sacrificial patterns interposed between the first dielectric layer and the insulating layers and including a material with a higher dielectric constant than the first dielectric layer.

The present technology includes a semiconductor memory device. The semiconductor memory device includes a stack including a conductive pattern and an insulating pattern, a channel structure penetrating the stack, and a memory pattern between the conductive pattern and the channel structure. The memory pattern includes a blocking pattern, a tunnel pattern, a storage pattern, and a ferroelectric pattern.

Semiconductor memory device and method of operating the semiconductor memory device

A semiconductor device according to an embodiment includes a substrate, and a gate structure disposed over the substrate. The gate structure includes a hole pattern including a central axis extending in a direction perpendicular to a surface of the substrate. The gate structure includes a gate electrode layer and an interlayer insulation layer, which are alternately stacked along the central axis. The semiconductor device includes a ferroelectric layer disposed adjacent to a sidewall surface of the gate electrode layer inside the hole pattern, and a channel layer disposed adjacent to the ferroelectric layer inside the hole pattern. In this case, one of the gate electrode layer and the interlayer insulation layer protrudes toward the central axis of the hole pattern relative to the other one of the gate electrode layer and the interlayer insulation layer.

Semiconductor device of three-dimensional structure including ferroelectric layer

The semiconductor memory device includes: a first substrate including a peripheral circuit, first conductive contact patterns connected to the peripheral circuit, and a first upper insulating layer having grooves exposing the first conductive contact patterns; a second substrate including a memory cell array, a second upper insulating layer disposed on the memory cell array, the second upper insulating layer formed between the memory cell array and the first upper insulating layer, second conductive contact patterns protruding through the second upper insulating layer into an opening of the grooves; and conductive adhesive patterns filling the grooves to connect the second conductive contact patterns to the first conductive contact patterns.

Growing community of inventors

Seoul, South Korea

Kun Young Lee