Taiwan Semiconductor Manufacturing Comp. Ltd.

Kun-Ming Huang

Po-Tao Chu

Shen-Ping Wang

Chien-Li Kuo

Chun-Yi Yang

Ming-Yi Lin

Long-Shih Lin

Chih-Heng Shen

Lieh-Chuan Chen

Fu-Hsiung Yang

Jheng-Sheng You

Hsin-Chih Lin

Cheng-Chi Chuang

Ming-Hong Chang

Tsai-Feng Yang

Tai-I Yang

Hong-Seng Shue

Hsuan-Hui Hung

Shao-Chi Yu

Paul Chu

Shou-Wei Lee

Hsueh-Liang Chou

Fu-Hsin Chen

Chen-Bau Wu

Yu-Chieh Chou

Yeh-Jye Wann

Ming-Che Yang

Che-Yi Lin

Tzu-Yang Wu

Weng-Chu Chu

Chi-Fu Lin

Eugene Chu

Cheng-Hsin Chen

Cheng-Wei Lee

Cheng-Fu Hsu

Ding-Jeng Yu

Chao-Wei Tseng

Yj Wang

Ying-De Chen

Ming-I Hsu

Tzu-Cheng Chen

An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

Passivation scheme for pad openings and trenches

A semiconductor arrangement includes a first well formed to a first depth and a first width in a substrate and a second well formed to a second depth and a second width in the substrate. The first well is formed in the second well, the first depth is greater than the second depth, and the second width is greater than the first width. A source region is formed in the second well and a drain region is formed in the substrate.

Semiconductor arrangement and method of making

A device includes a first III-V compound layer, a second III-V compound layer, source and drain structures, a gate structure, and a gate field plate. The second III-V compound layer is over the first III-V compound layer. The source and drain structures are over the second III-V compound layer and spaced apart from each other. The gate structure is over the second III-V compound layer and between the source and drain structures. The gate field plate is over the second III-V compound. From a top view the gate field plate forms a strip pattern interposing a stripe pattern of the gate structure and a stripe pattern of the drain structure.

Semiconductor device

A device includes a first III-V compound layer, a second III-V compound layer, a dielectric layer, a contact, a metal-containing layer, and a metal contact. The second III-V compound layer is over the first III-V compound layer. The dielectric layer is over the second III-V compound layer. The contact extends through the dielectric layer to the second III-V compound layer. The contact is in contact with a top surface of the dielectric layer and an inner sidewall of the dielectric layer. The metal-containing layer is over and in contact with the contact, and a portion of the metal-containing layer is directly above the dielectric layer. The metal contact is over and in contact with the metal-containing layer.

A high electron mobility transistor (HEMT) includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, source and drain structures over the second III-V compound layer and spaced apart from each other, a gate structure over the second III-V compound layer and between the source and drain structures, a gate field plate over the second III-V compound layer and between the gate structure and the drain structure, and an etch stop layer over the drain structure and spaced apart from the gate field plate.

A bipolar transistor includes a substrate having a first well with a first dopant type; and a split collector region in the substrate, the split collector region including a highly doped central region having the first dopant type, and a lightly doped peripheral region having a second dopant type, opposite the first dopant type, wherein the lightly doped peripheral region surrounds the highly doped central region, a dopant concentration of the lightly doped peripheral region ranges from about 5&#xd7;10ions/cmto about 5&#xd7;10ions/cm, and the lightly doped peripheral region has a same maximum depth as the highly doped central region.

Method of making bipolar transistor

The method comprises forming a drain region in the first layer. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The method also comprises forming a source region free from contact with and surrounding the drain region in the first layer.

Ultra high voltage semiconductor device with electrostatic discharge capabilities

A method of making a bipolar transistor includes patterning a first photoresist over a collector region of the bipolar transistor, the first photoresist defining a first opening. The method further includes performing a first implantation process through the first opening. The method further includes patterning a second photoresist over the collector region, the second photoresist defining a second opening different from the first opening. The method further includes performing a second implantation process through the second opening, wherein a dopant concentration resulting from the second implantation process is different from a dopant concentration resulting from the first implantation process.

A semiconductor device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a source contact and a drain contact over the second III-V compound layer, a gate contact over the second III-V compound layer and between the source contact and the drain contact, a gate field plate over the second III-V compound layer, a first etch stop layer over the source contact, and a second etch stop layer over the drain contact and separated from the first etch stop layer.

A device having a drain region with a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The semiconductor device also comprises a source region spaced from and surrounding the drain region in the first layer.

A method for manufacturing semiconductor device includes depositing a contact metal layer over a III-V compound layer. An anti-reflective coating (ARC) layer is deposited over the contact metal layer, and an etch stop layer is deposited over the ARC layer. The etch stop layer, the ARC layer, and the contact metal layer are etched to form a contact stack over the III-V compound layer. A conductive layer is deposited over the III-V compound layer, and the conductive layer is etched to form a gate field plate. The etch stop layer has an etch selectivity different from that of the conductive layer.

Method for fabricating semiconductor device

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Taipei, Taiwan

Kun-Ming Huang