Bell Communications Research, Inc.

Graphics Communication Technologies, Ltd.

Kun-Min Yang

Hiroshi Fujiwara

Ming-Ting Sun

Kou-Hu Tzou

Lancelot Wu

Toshifumi Sakaguchi

Akio Shimatzu

A variable-length codeword encoder is disclosed which produces 8-bit output segments for storage in a buffer (23) for subsequent transmission over a transmission channel (24). The encoder includes two memory tables (15, 16), which produce in response to each input symbol to be encoded, a variable-length codeword and an a codeword length. An accumulator (31, 33) accumulates, modulo-8, the successive codeword lengths, producing a carry signal during any clock cycle in which eight or more bits codeword bits are accumulated. At each clock cycle, the variable-length codeword is input to the parallel inputs of a cross bar shift control circuit (30). This shift control circuit produces a 16-bit output in which the input word is embedded. The input word is shifted in the 16-bit output from the more significant bit positions to the less significant positions by a shift value determined from previous accumulated codeword lengths, with the shift value number of '0' bits being inserted in the more significant bit positions preceding the codeword. An OR circuit (38) combines the shifted variable-length codeword with previous variable-length codeword bits to form a concatenated sequence which is stored in upper and lower latches (53, 54). At any clock cycle, when the number of accumulated codeword bits is less than eight, the concatenated bits stored in the first and second latches are fed back to the OR circuit for combination at the next clock cycle with the next shifted variable-length codeword. When eight or more codeword bits are accumulated, the accumulator produces a carry signal and the 8-bit segment in the upper latch is outputted. The 8-bits in the lower latch are then shifted to the more significant bit positions of a concatenated sequence that is fed back to the OR circuit for combination with the next shifted variable-length codeword.

Variable-length codeword encoder

A circuit for carrying out a full search block matching algorithm with fractional pixel precision comprises a first subcircuit for obtaining displacement vectors with integer pixel value precision and a second subcircuit for correcting the displacement vectors obtained by the subcircuit so that the displacement vectors have fractional pixel value precision. To obtain a displacement vector with integer value precision for a block of pixels of a current video frame in a search area of a previous video frame, the first subcircuit finds a first specific position of the block with the smallest error out of a first plurality of positions defined by integer pixel values in the search area. The second subcircuit interpolates the integer pixel values of the first specific position to obtain fractional pixel values which define a second plurality of positions in the search area. The second subcircuit then determines which position of the block in the second plurality of positions has the smallest error, thereby providing a correction with fractional pixel precision for the displacement vector.

Circuit implementation of block matching algorithm with fractional

A circuit for implementing a full search block matching algorithm for coding video signals sequentially receives pixel values from a block of pixels in a current video frame and sequentially receives pixel values from a search area of a previous video frame. The circuit includes a plurality of processors for calculating in parallel a group of error functions corresponding to a group of positions of the block in the search area. The error functions are compared for determining the block position having the minimum error function.

Circuit implementation of block matching algorithm

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Somerville, NJ, United States of America

Kun-Min Yang