Lextar Electronics Corporation

Powerchip Semiconductor Corporation

Kun-Jung Wu

Dao-Wei Chen

Yu-Chi Lin

Bo-Yu Ko

Huang-Yi Lin

Nagai Yukihiro

Ju-Hsin Chi

Pin-Yuan Yu

Yung-Chih Lin

A frame includes first and second leads and a body. The first and second leads contain a metal material. The body contains a non-metal material and has first and second side surfaces. The first and second leads are covered with the body. The first and second leads extend in a first direction to outwardly protrude from the body. The first and second side surfaces are respectively abutted against two ends of the protruding first lead and respectively slanted to the two ends of the protruding first lead by a first angle &#x3b8;and a second angle &#x3b8;which are defined by the following relationship, &#x3b8;&#x2260;0&#xb0; and the &#x3b8;&#x2260;180&#xb0;, and the &#x3b8;&#x2260;0&#xb0; and the &#x3b8;&#x2260;180&#xb0;. The substance between any two points in each of the first and second side surfaces is non-metal.

Frame, light-emitting device using the same, and method for manufacturing the same

An LED package structure includes a first metal plate, a second metal plate, and a mold. The first metal plate has at least one first protrusion portion. The second metal plate has at least one second protrusion portion. The mold is disposed on the first metal plate and the second metal plate, in which the mold has a first side surface, a second side surface opposite to the first side surface, a third side surface, and a fourth side surface opposite to the third side surface. The first and second protrusion portion protrude respectively from the first side surface and the second side surface, and the first metal plate and the second metal plate are covered by the third side surface and the fourth side surface, in which a portion of the first side surface between the first edge and the first protrusion portion is a fracture surface.

LED package structure

Light emitting diode lead-frame

Light emitting diode package

A process for fabricating crown capacitors is described. A substrate having a template layer thereon is provided. A patterned support layer is formed over the template layer. A sacrifice layer is formed over the substrate covering the patterned support layer. Holes are formed through the sacrifice layer, the patterned support layer and the template layer, wherein the patterned support layer is located at a depth at which bowing of the sidewalls of the holes occurs and is bowed less than the sacrifice layer at the sidewalls. A substantially conformal conductive layer is formed over the substrate. The conductive layer is then divided into lower electrodes of the crown capacitors.

Process for fabricating crown capacitors of dram and capacitor structure

A method of piping defect detection is provided. A semiconductor substrate having an active region and an isolation region is provided, a plurality of semiconductor elements are formed on the semiconductor substrate, a dielectric layer is deposited on the semiconductor substrate and the semiconductor elements, and first and second contact plugs are formed in the dielectric layer to connect the active region and the isolation region respectively. The first contact plug and the second contact plug are illuminated by an electron beam, accumulating charge on the second contact plug, and piping defects are detected between the first contact plug and the second contact plug according to brightness contrast between the first contact plug and the second contact plug.

Method of piping defect detection

A method of manufacturing semiconductor devices. A gate structure is formed over a substrate. A dopant implantation is carried out to form a lightly doped region in the substrate on each side of the gate structure. An insulation layer is formed over the substrate. A portion of the insulation is later removed so that a portion of the insulation layer is retained over the substrate on each side of the gate structure. A spacer is formed on each sidewall of the gate structure. Another ion implantation is carried out such that the dopants penetrate through the insulation layer on the substrate on each side of the gate structure to form a heavily doped region in the substrate.

Method of manufacturing semiconductor device with formation of a heavily doped region by implantation through an insulation layer

A method of manufacturing a memory device. A substrate having an active region, a plurality of gate structures and a plurality of source/drain regions are provided. An inter-layer dielectric layer is formed over the substrate. A global opening that exposes the source/drain regions for forming contacts and the gate structures inside the active region is formed in the inter-layer dielectric layer. A conductive layer that completely fills the global opening is formed over the substrate. A portion of the conductive layer and the inter-layer dielectric layer is removed to expose the upper surface of the gate structures, thereby forming a plurality of contacts between the gate structures.

Growing community of inventors

Hsinchu, Taiwan

Kun-Jung Wu