Amazing Microelectronic Corporation

Industrial Technology Research Institute

United Microelectronics Corp.

National Yang Ming Chiao Tung University

Amazing Microelectronics Corp.

Vanguard International Semiconductor Corporation

National Sun Yat-sen University of Kaohsiung

Kun-Hsien Lin

Che-Hao Chuang

Ryan Hsin-Chin Jiang

Zi-Ping Chen

Hsin-Fu Huang

Ming-Dou Ker

Chin-Fu Lin

Chi-Mao Hsu

Chih-wei Chen

Yi-Yuan Chen

Xin-Lan Liao

Po-Yu Huang

Lih-Guong Jang

Tun-Chih Yang

Chun-Yuan Wu

Tzung-Ying Lee

Shih-Hung Chen

Mei-Lian Fan

Chi-Neng Liu

Min-Chuan Tsai

Chih-Ting Yeh

Kuan-Yu Lin

Yu-Shu Shen

Wei-Liang Wu

Chun-Hsien Lin

Chia-Lin Hsu

Chien-Ming Lai

Che-Hua Hsu

Zhi-Cheng Lee

Tung-Yang Chen

Geeng-Lih Lin

Yi-Wen Chen

Hsin-Chin Jiang

Tong-Jyun Huang

Ken-Huang Lin

Chun-Yih Wu

Yi-Chang Molly Wang

Hung-Hsuan Lin

Nien-Chu Wu

Tang-Kuei Tseng

Yu-Feng Yeh

Wen-Chieh Su

Yao-Tai Tseng

Che-hao Chuang

Sung Chih Huang

Chih-Wei Chen

Lih-Goung Jang

Tai-Shen Ho

A transient voltage suppression device includes at least one N-type lightly-doped structure, a first P-type well, a second P-type well, a first N-type heavily-doped area, and a second N-type heavily-doped area. The first P-type well and the second P-type well are formed in the N-type lightly-doped structure. The first N-type heavily-doped area and the second N-type heavily-doped area are respectively formed in the first P-type well and the second P-type well. The doping concentration of the first P-type well is higher than that of the second P-type well. The first P-type well and the second P-type well can be replaced with P-type lightly-doped wells respectively having P-type heavily-doped areas under the N-type heavily-doped areas.

Transient voltage suppression device

A diode test module and method applicable to the diode test module are provided. A substrate having first conductivity type and an epitaxial layer having second conductivity type on the substrate are formed. A well region having first conductivity type is formed in the epitaxial layer. A first and second heavily doped region having second conductivity type are theoretically formed in the well and connected to a first and second I/O terminal, respectively. Isolation trench is formed there in between for electrical isolation. A monitor cell comprising a third and fourth heavily doped region is provided in a current conduction path between the first and second I/O terminal when inputting an operation voltage. By employing the monitor cell, the invention achieves to determine if the well region is missing by measuring whether a leakage current is generated without additional testing equipment and time for conventional capacitance measurements.

Diode test module for monitoring leakage current and its method thereof

A bidirectional electrostatic discharge protection device includes at least one bipolar junction transistor and at least one silicon-controlled rectifier. The silicon-controlled rectifier is coupled to the bipolar junction transistor in series. The absolute value of the breakdown voltage of the bipolar junction transistor is lower than that of the silicon-controlled rectifier and the absolute value of the holding voltage of the bipolar junction transistor is higher than that of the silicon-controlled rectifier when an electrostatic discharge voltage is applied to the bipolar junction transistor and the silicon-controlled rectifier.

Bidirectional electrostatic discharge (ESD) protection device

A bidirectional electrostatic discharge protection device includes a first transient voltage suppressor chip, a second transient voltage suppressor chip, a first conductive wire, and a second conductive wire. The first transient voltage suppressor chip includes a first diode and a first bipolar junction transistor. The first diode and the first bipolar junction transistor are electrically connected to a first pin. The second transient voltage suppressor chip includes a second diode and a second bipolar junction transistor. The second diode and the second bipolar junction transistor are electrically connected to a second pin. The first conductive wire is electrically connected between the first diode and the second bipolar junction transistor. The second conductive wire is electrically connected between the second diode and the first bipolar junction transistor.

A multi-channel transient voltage suppression device includes a semiconductor substrate, a semiconductor layer, at least two bidirectional transient voltage suppression structures, and at least one isolation trench. The semiconductor substrate, having a first conductivity type, is coupled to a grounding terminal. The semiconductor layer, having a second conductivity type opposite to the first conductivity type, is formed on the semiconductor substrate. The bidirectional transient voltage suppression structures are formed in the semiconductor layer. Each bidirectional transient voltage suppression structure is coupled to an input/output (I/O) pin and the grounding terminal. The isolation trench is formed in the semiconductor substrate and the semiconductor layer and formed between the bidirectional transient voltage suppression structures. The isolation trench has a height larger than the height of the semiconductor layer and surrounds the bidirectional transient voltage suppression structures.

Multi-channel transient voltage suppression device

A transient voltage suppression device includes at least one P-type lightly-doped structure and at least one electrostatic discharge structure. The electrostatic discharge structure includes an N-type lightly-doped well, an N-type well, a first P-type heavily-doped area, and a first N-type heavily-doped area. The N-type lightly-doped well is formed in the P-type lightly-doped structure. The N-type well is formed in the N-type lightly-doped well. The doping concentration of the N-type lightly-doped well is less than that of the N-type well. The first P-type heavily-doped area is formed in the N-type well. The first N-type heavily-doped area is formed in the P-type lightly-doped structure.

State estimation and sensor fusion switching methods for autonomous vehicles thereof are provided. The autonomous vehicle includes at least one sensor, at least one actuator and a processor, and is configured to transfer and transport an object. In the method, a task instruction for moving the object and data required for executing the task instruction are received. The task instruction is divided into a plurality of work stages according to respective mapping locations, and each of the work stages is mapped to one of a transport state and an execution state, so as to establish a semantic hierarchy. A current location of the autonomous vehicle is detected by using the sensor and mapped to one of the work stages in the semantic hierarchy, so as to estimate a current state of the autonomous vehicle.

State estimation and sensor fusion switching methods for autonomous vehicles

A transient voltage suppression device includes a P-type semiconductor layer, a first N-type well, a first N-type heavily-doped area, a first P-type heavily-doped area, a second P-type heavily-doped area, and a second N-type heavily-doped area. The first N-type well and the second N-type heavily-doped area are formed in the layer. The first P-type heavily-doped area is formed in the first N-type well. The first P-type heavily-doped area is spaced from the bottom of the first N-type well. The second P-type heavily-doped area is formed within the first N-type well and spaced from the sidewall of the first N-type well. The second P-type heavily-doped area is formed between the first P-type heavily-doped area and the second N-type heavily-doped area.

A voucher verification auxiliary method is provided, including: when a user device is approaching a voucher verification auxiliary device, generating an encryption key for the user device to encrypt voucher data with the encryption key to generate first encrypted data; reading and decrypting the first encrypted data to obtain the voucher data; encrypting the voucher data to generate and transmit second encrypted data to a verification center; decrypting the second encrypted data to obtain the voucher data, generating a verification result after verifying the voucher data, encrypting the verification result to become third encrypted data, and transmitting the third encrypted data back to the voucher verification auxiliary device; decrypting the third encrypted data to obtain the verification result; transmitting the verification result to a voucher receiving terminal. A voucher verification auxiliary device and a voucher verification auxiliary system are also provided.

Voucher verification auxiliary device, voucher verification auxiliary system, and voucher verification auxiliary method

A bidirectional electrostatic discharge protection device and a method for fabricating the same is disclosed. The protection device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, a second semiconductor epitaxial layer, a heavily-doped area, and a lightly-doped area. The substrate, the heavily-doped area, and the lightly-doped area have a first conductivity type and the epitaxial layers have a second conductivity type. The first semiconductor epitaxial layer and the second semiconductor epitaxial layer are sequentially formed on the substrate, and the heavily-doped area and the lightly-doped area are formed in the second semiconductor epitaxial layer. The lightly-doped area covers the corner of the heavily-doped area, and the breakdown voltage of a junction between the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer corresponds to the breakdown voltage of a junction between the second semiconductor epitaxial layer and the heavily-doped area.

An embedded NMOS triggered silicon controlled rectification device includes a P-type substrate, at least one rectifying zone, and at least one trigger. The rectifying zone includes a first N-type heavily doped area, an N-type well, and a first P-type heavily doped area. Alternatively, the device includes an N-type substrate, a first P-type well, at least one rectifying zone, and at least one trigger. The rectifying zone includes a second P-type well, a first N-type heavily doped area, and a first P-type heavily doped area. The trigger cooperates with the P-type substrate or the first P-type well to form at least one NMOSFET. The trigger is independent to the rectifying zone. The first P-type heavily doped area is arranged between the trigger and the first N-type heavily doped area.

Embedded N-channel metal oxide semiconductor (nmos) triggered silicon controlled rectification device

A transient voltage suppression device includes a lightly-doped semiconductor structure, a first doped well, a first heavily-doped area, a first buried area, and a second heavily-doped area. The lightly-doped semiconductor structure has a first conductivity type. The first doped well has a second conductivity type and is formed in the lightly-doped semiconductor structure. The first heavily-doped area has the second conductivity type and is formed in the first doped well. The first buried area has the first conductivity type and is formed in the lightly-doped semiconductor structure and under the first doped well, and the first buried area is adjacent to the first doped well. The second heavily-doped area has the second conductivity type and is formed in the lightly-doped semiconductor structure.

A vertical transient voltage suppression device includes a semiconductor substrate having a first conductivity type, a first doped well having a second conductivity type, a first heavily-doped area having the first conductivity type, a second heavily-doped area having the first conductivity type, and a diode. The first doped well is arranged in the semiconductor substrate and spaced from the bottom of the semiconductor substrate, and the first doped well is floating. The first heavily-doped area is arranged in the first doped well. The second heavily-doped area is arranged in the semiconductor substrate. The diode is arranged in the semiconductor substrate and electrically connected to the second heavily-doped area through a conductive trace.

Vertical transient voltage suppression device

A lateral transient voltage suppressor device is provided, comprising a doped substrate, a lateral clamping structure disposed on the doped substrate, a buried doped layer disposed between the doped substrate and the lateral clamping structure for isolation, at least one diode module, and at least one trench arranged in the doped substrate, having a depth not less than that of the buried doped layer, and being disposed between the lateral clamping structure and the at least one diode module for electrical isolation. The doped substrate and the buried doped layer have opposite conductivity types such that the doped substrate is electrically floating. The buried doped layer can be further disposed to separate the diode module from the doped substrate. By employing the proposed invention, the lateral transient voltage suppressor device is advantageous of maintaining both a lower clamping voltage as well as a reduced dynamic resistance.

Lateral transient voltage suppressor device

A method and an apparatus for establishing a coordinate system and a data structure product are provided. The method includes following steps: obtaining at least one layer related to an arrangement of an indoor space to generate a layout pattern in a 2D or 3D model; obtaining locations of positioning devices located within the indoor space and labelling the locations in the layout pattern; dividing the layout pattern into multiple view tiles according to a unit area or a unit volume for displaying the layout pattern; dividing a portion of the layout pattern around the labelled positioning devices into multiple positioning tiles according to the labelled locations of the positioning devices; and selecting at least one representative point of the view tiles and the positioning tiles as a reference point to define a reference frame and establishing the coordinate system based on the reference frame.

Method and apparatus for establishing coordinate system and data structure product

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Hsinchu, Taiwan

Kun-Hsien Lin