Au Optronics Corporation

Kun-Hong Chen

Chinwei Hu

Yang-En Wu

Wen-Rei Guo

Chun-Ching Wei

Ming-Yan Chen

Chang-Cheng Lo

Chin-Wei Hu

Kuang-Chao Yeh

Tzu-Wei Ho

Hung-Hsiao Lin

A structure for encapsulating a liquid crystal display device is disclosed. Openings are formed in a second material layer on a first substrate, exposing an underlying first material layer. The openings are substantially distributed over the perimeter of the first substrate. A sealant is placed in the openings, forming a sealant region for attachment of a second substrate to the first substrate. The sealant region is substantially perpendicular to a direction of length of the openings. In addition, the sealant contacts the first material layer and the second material layer through the openings.

Structure for encapsulating a liquid crystal display device

A fan-out wire structure is used to connect a driver and a display region of a display panel and has a plurality of first single-layer wires and at least one second single-layer wire. The first ends of the first single-layer wires are connected to the driver, and the second ends of the first single-layer wires are connected to the display area. The first end of the second single-layer wire is connected to the driver, and the second end of the second single-layer wire is connected to the display area. A metal layer of the first single-layer wires is different from a metal layer of the second single-layer wire.

Fan-out wire structure for a display panel

Display panels capable of eliminating reliability issues due to high switching frequency. The display panel comprises a data driver outputting first, second, third and fourth data signals in sequence through a data line, a scan driver outputting first and second scan signals in sequence through first and second scan lines and an auxiliary driver generates first and second auxiliary signals in sequence, and first and second display cells commonly receives the first scan signal through the first scan line and receives the first and the second data signal through the data line, and a first switch is coupled to the data line and the second display cell, turning on and off in sequence according to the first auxiliary signal when the first scan signal is applied thereto such that the second and the first display cells receive the first and the second data signals in sequence.

Display panels

An asymmetry thin-film transistor includes a substrate, a semiconductor layer positioned on the substrate, and a gate positioned on the substrate. The semiconductor layer has a channel region, a single lightly doped region and a first heavily doped region positioned at a side of the channel region, and a second heavily doped region positioned at the other side of the channel region. The semiconductor layer has a central line extending through the semiconductor layer and the substrate, the first heavily doped region and the second heavily doped region have equal lengths and are symmetric with respect to the central line of the semiconductor layer, and the gate is asymmetric with respect to the central line of the semiconductor layer. There is no lightly doped region in between the channel region and the second heavily doped region.

Asymmetry thin-film transistor

An interconnect structure connecting two isolated metal lines in a non-display area of a TFT-array substrate. A first metal line is disposed on the substrate, covered with a first insulating layer. A second metal line is disposed on the first insulating layer and covered by a second insulating layer. ITO (indium tin oxide) wiring is disposed on the second insulating layer, electrically connecting the first and second metal lines. A passivation structure is disposed on the second insulating layer, with an opening therein to expose and surround the ITO wiring.

Interconnect structure for TFT-array substrate and method for fabricating the same

A bonding pad structure on marginal area of a substrate of a liquid crystal display comprises a plurality of bonding pads and insulations. The bonding pads defined at the time of forming a gate on pixel area of the substrate are located on marginal area of the substrate, whereas the insulations defined at the time of forming a dielectric layer to cover the gate are sandwiched between the bonding pads.

Bonding pad and method for manufacturing the same

The present invention discloses a control TFT structure (i.e. a driving TFT) for reducing leakage in an OLED display. A semiconductor layer, such as a polysilicon layer, is deposited on a transparent substrate as a channel region. A lightly doped region and a drain region are disposed on one side of the polysilicon layer and a source region is disposed on the opposite side of the polysilicon layer. An insulating layer is deposited covering the surface of the polysilicon layer, the lightly doped region, and the source/drain regions. Source and drain electrodes are disposed in the insulating layer, electrically connecting the source and drain region respectively. A gate metal layer is disposed on the insulating layer, at approximately the top right portion of the polysilicon layer to form a transistor structure.

Control TFT for OLED display

An asymmetry thin-film transistor includes a substrate, a semiconductor layer and a gate positioned on the substrate. The semiconductor layer includes a first lightly doped region and a first heavily doped region adjacent to a first gate side, and a second lightly doped region together with a second heavily doped region adjacent to a second gate side. A first junction is between the first lightly doped region and the first heavily doped region. A second junction is between the second lightly doped region and the second heavily doped region. A distance between the first junction and the first gate side is unequal to a distance between the second junction and the second gate side.

A pixel structure of active organic light emitting diode is disclosed, which comprises an organic light emitting diode, a data-line, a scan-line, a switch thin film transistor (TFT), a control TFT, and a capacitor. The switch TFT has a first lightly doping drain and the control TFT has a second lightly doping drain. The doped concentration of the second lightly doped drain region is higher than that of the first lightly doped drain region. The leakage current in the switch TFT is reduced and the kink effect in the control TFT is improved by the pixel structure of an active organic light emitting diode. Therefore, a better display performance is provided.

Pixel structure of active organic light emitting diode

A method of forming a CMOS transistor on a substrate is provided, wherein the method requires only two implanting procedures to form all source/drain and light doped region. First, the source/drain of an NMOS transistor is formed by using a photoresist layer which covers up the source/drain of a PMOS transistor as a mask with a phosphorus dopant being implanted into. Next, the lightly doped region of an NMOS transistor and the source/drain of a PMOS transistor are formed by using a photoresist layer which covers up the source/drain of an NMOS transistor as well as the gate as masks with a boron dopant being implanted into. Of which, the dosage of the boron dopant is smaller than that of the phosphorus dopant.

Method of forming a CMOS transistor

A thin-film transistor liquid crystal display (TFT-LCD) substrate mainly includes a substrate and a planarization layer thereon. The substrate is defined to form a thin-film transistor (TFT) and a contact plug thereon and the source/drain of the TFT is electrically coupled with the contact plug. The planarization layer is disposed on the substrate and the planarization layer has a via hole for penetrating the planarization layer to expose to the contact plug. The configuration of the cross-section of the via hole includes a straight edge so that the via hole is able to be formed with a less steep taper at a lateral view by reflow.

Thin-film transistor liquid crystal display substrate

A polysilicon thin film transistor and a method of forming the same is provided. A poly-island layer is formed over a substrate. A gate insulation layer is formed over the poly-island layer. A gate is formed over the gate insulation layer. Using the gate as a mask, an ion implantation of the poly-island layer is carried out to form a source/drain region in the poly-island layer outside the channel region. An oxide layer and a silicon nitride layer, together serving as an inter-layer dielectric layer, are sequentially formed over the substrate. Thickness of the oxide layer is thicker than or the same as (thickness of the nitride layer multiplied by 9000 &#x212b;)and maximum thickness of the nitride layer is smaller than 1000 &#x212b;.

Growing community of inventors

Taipei Hsien, Taiwan

Kun-Hong Chen