Samsung Electronics Co., Ltd.

Kun-gu Lee

Jeong-Ho Bang

Kwang-Kyu Bang

Kyeong-seon Shin

Kwang-kyu Bang

Ho-Jeong Choi

Jeong-kyu Kim

Tai-Heui Cho

Seung-Gyoo Choi

Kyoung-Suk Lyu

Provided are a fuse box that simultaneously prevents damage caused by laser blowing and cross talk between the fuses and a method of manufacturing the same. In a fuse box having an open region in which fuses are opened by laser blowing and a bundle region in which fuse opens do not occur, a capping layer, adjacent to the open region, having a metal layer and an insulation layer covers the outermost fuses in the bundle region, thereby reducing the influence of laser blowing of fuses in the bundle region, and preventing capacitive coupling caused by the formation of a parasitic capacitor between fuse lines and an insulation layer therebetween. Accordingly, cross talk due to the capacitive coupling can be prevented, thereby enhancing the reliability of a fuse circuit. Lower fuses can be disposed in a lower layer in the bundle region, thereby forming a two-layered fuse box.

Fuse box reducing damage caused by laser blowing and cross talk

A semiconductor device includes a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and a first capping pattern, an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse pattern, and a second insulating layer formed on the first insulating layer and covering the fuse pattern.

Semiconductor device having fuse pattern and methods of fabricating the same

A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.

Fuse regions of a semiconductor memory device and methods of fabricating the same

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Seoul, South Korea

Kun-gu Lee