Taiwan Semiconductor Manufacturing Comp. Ltd.

Kun-Ei Chen

Chen-Chieh Chiang

Ling-Sung Wang

Shiu-Ko JangJian

Chun-Che Lin

Chung-Ren Sun

Jen-Yi Chen

Chih-Han Lin

Huai-Tei Yang

Chien-Chung Chen

Jun-Nan Nian

I-i Cheng

Chun-Yuan Hsu

Hsueh-Han Lu

Yu-Yi Wu

Hsu Tung Yen

Bo Hsiang Huang

Yi-Chung Lin

Pei-Lum Ma

San-Ching Lin

The present disclosure describes a semiconductor device having an isolation structure with a protection layer. The semiconductor device includes a substrate, a transistor with a source/drain (S/D) structure on the substrate, and an isolation structure on the substrate and adjacent to the transistor. The isolation structure includes a dielectric structure on the substrate, a protection layer on the dielectric structure, and a gate structure on the protection layer. The protection layer is disposed between the gate structure and the S/D structure.

Isolation structures for semiconductor devices

A work piece holder provided herein includes a support baffle and an elevating element. The support baffle extends along an arc path. The elevating element is disposed on the support baffle and is pivoted to be movable between an unlock status and a lock status.

Work piece holder and method of transferring a work piece

Semiconductor device structure and methods of forming the same are described. The structure includes a first dielectric layer including a first portion disposed over a source/drain region in an active region of a substrate and a modulation portion over an interlayer dielectric (ILD) in a resistor region of the substrate, the first portion of the first dielectric layer has a first composition, and the modulation portion of the first dielectric layer has a second composition different from the first composition. The structure further includes a resistor layer disposed on the modulation portion of the first dielectric layer in the resistor region and a second dielectric layer disposed over the first dielectric layer in the active region and over the resistor layer in the resistor region.

Semiconductor device structure and methods of forming the same

A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.

Semiconductor device with contamination improvement

A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions disposed in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.

Method for manufacturing semiconductor device with contamination improvement

A method of semiconductor processing comprises providing a semiconductor wafer in a processing chamber; feeding at least one tungsten-containing precursor in a gas state into the processing chamber for atomic layer deposition (ALD) of tungsten; feeding at least one reducing chemical in a gas state into the processing chamber; and monitoring a concentration of at least one gaseous byproduct in the chamber; and providing a signal indicating concentration of the at least one gaseous byproduct in the chamber. The byproduct is produced by a reaction between the at least one tungsten-containing precursor and the at least one reducing chemical during the ALD.

System and method of monitoring and controlling atomic layer deposition of tungsten

A device includes a semiconductor substrate having a front side and a backside. An active image sensor pixel array is disposed on the front side of the semiconductor substrate. A metal shield is disposed on the backside of, and overlying, the semiconductor substrate. The metal shield has an edge facing the active image sensor pixel array. The metal shield has a middle width, and a top width greater than the middle width.

Metal shield structures in backside illumination image sensor chips

A method of patterning a material layer of a semiconductor device is disclosed, the method including treating a material layer above a semiconductor substrate with plasma oxygen; depositing a layer of photoresist over a first surface of the material layer after the treating of the material layer; patterning the layer of photoresist, thereby forming a patterned photoresist, exposing portions of the material layer; etching the exposed portions of at least the material layer to form at least one contact via in the material layer extending to a source or drain region of a device at a surface of the substrate; and removing the patterned photoresist from the first surface of the material layer.

Method for forming semiconductor device

A method of forming a dual damascene includes forming first, second and third material layers sequentially over a substrate. The first, second and third material layers have first, second and third thicknesses, respectively. An opening is etched within the first material layer while a portion or all of the thickness of the third layer is simultaneously removed. The ratio of the depth of the opening and the thickness of the third material layer removed, correspond to an etch selectivity of the first material layer and the second material layer. The etching operation may be automatically terminated to produce the opening with a predetermined depth.

Method of forming dual damascene semiconductor device

An apparatus and method for detecting mispositioned wafers attributable to transfer shift of the wafer are disclosed. A calibration wafer has a target region comprising a pattern of optically distinguishable features from which is determined the position of the calibration wafer within the chamber subsequent to its transfer therein. Preferably, the features comprise a pattern of colors that can be detected by spectroscopy. A preferred form and manner of providing such color features is by way of dielectric thin film filters.

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Tainan, Taiwan

Kun-Ei Chen