United Microelectronics Corp.

Kun-Cho Chen

Heng-Sheng Huang

Jason Jyh-shyang Jenq

H C Tseng

Sun-Chieh Chien

Der-Yuan Wu

Meng-Jin Tsai

Mu-Chun Wang

Shiang Huang-Lu

A wafer acceptance testing (WAT) method with a test key is provided. The test key structure includes a testing structure on a substrate. An inter-layer-dielectric layer covers over the substrate to isolate the testing structure. A grounded metal layer is located on the inter-layer dielectric layer. An interconnecting structure is located on the grounded metal layer. A conductive pad layer and a passivation layer are sequentially located on the interconnecting structure. The testing structure is electrically coupled to the interconnecting structure. The interconnecting structure is also electrically coupled to the conductive pad layer. The grounded metal layer is grounded without any further coupling such that the grounded metal layer is not coupled to the testing structure and the interconnecting structure.

Wafer acceptance testing method and structure of a test key used in the method

A wafer structure on an IC chip allows the bonding pads on the IC chip to be firmly secured to the IC chip, thereby preventing detachment of the bonding pads during assembly of the IC package. The wafer structure comprises a substrate on which at least a pad area is defined. The pad area is formed with a first insulating layer, a gate on the first insulating layer, a second insulating layer on the gate, and a third insulating layer on the second insulating layer. The second insulating layer has a plurality of lower openings formed therethrough and the third insulating layer has a plurality of upper openings formed therethrough, each upper opening corresponding to one of the lower openings. The lower openings are wider than the upper openings. Plugs are formed in the lower and upper openings and are bonded to a metallization layer which serves as a bonding pad for the IC chip. The wider lower part of the plugs allows them to be rigidly affixed within the openings, thus allowing the overlaying bonding pad to be firmly secured to the IC chip. Therefore, during assembly of the IC chip, the bonding pad is not readily detached from the IC chip, thus increasing the assembly yield of good IC packages.

Wafer structure for securing bonding pads on integrated circuit chips

A planarization method for self-aligned contact process which is suitable for use in DRAM processing. Prior to the formation of the bottom terminal layer of the capacitor, the substrate surface is first planarized, thus avoiding stringer effects and related bridging problems arising from an undulating surface profile, during subsequent etching of the defined pattern. Also according to the method of this invention, by covering the silicon substrate that has MOS transistors laid on top with first a deposition of an oxide layer, then an etch discriminatory layer, and finally a planarization layer, a substrate with a smooth, plane surface is obtained.

Planarization method for self-aligned contact process

A MOSFET device protects the device from the short channel effect and decrease the resistance of a gate of the device. The MOSFET device includes a gate formed on a substrate and two source/drain regions. The source/drain regions are formed in the substrate at the sides of the gate. An oxide layer includes a first structure and a second structure. The first structure is at the side walls of the gate with the top of the first structure being lower than the top of the gate. The second structure is formed on the substrate and is connected to the first structure. A first spacer is formed on the second structure and beside the first structure. A second spacer is formed on the second structure and beside the first spacer. A self-aligned metal layer is formed on the gate, the first spacer, and over the substrate. As a result, the MOSFET device has an ultra-shallow junction under the first spacer to reduce the source/drain resistance and increase the operating rate of the device.

MOSFET device with two spacers

Bonding pad structures may be fabricated by forming a layered structure including a first conducting layer and first and second insulating layers on top of a substrate. Openings are etched through the first and second insulating layers, with the openings being wider in the first insulating layer than in the second insulating layer. The etching process may be carried out in two steps, with the second step preferentially isotropically etching the first insulating layer so that the openings are wider in the first insulating layer than in the second insulating layer and a portion of the second insulating layer overhangs the opening above the first insulating layer. Metal is then deposited within the openings and on top of the second insulating layer. An interlocking structure is formed with the conducting material extending underneath of the overhang portions of the second insulating layer. A passivation layer may be formed over the conducting material. The conducting material may include a barrier layer, a plug, and a top bond pad layer.

Method and structure for preventing bonding pad peel back

A manufacturing method applicable for forming a via connection to the thin film transistor in a SRAM unit which resolves the problems arising from a conventional method for forming a via for linking up the drain of a load transistor with the gate of a driver transistor in a SRAM unit by changing the processing sequence and also by forming a plug instead of a via.

Method for forming poly-via connection between load transistor drain and

A method of fabricating a MOSFET device in accordance with the present invention can protect the device from the short channel effect and decrease the resistance of a gate of the device. The fabricating method includes the following steps. A device including a substrate, an oxide layer, a gate and a lightly doped region is provided, wherein the oxide layer is formed on the substrate and the gate is formed on the oxide layer. A conducting layer is formed on the oxide layer, and the conducting layer is etched to form a first spacer. Then, the device is implanted to form a heavily doped region. A dielectric layer is deposited on the device, and the dielectric layer is etched to form a second spacer. The oxide layer is etched to expose part of the side walls of the gate. Then, a self-aligned silicide is further processed to complete the fabricating processes. As a result, the MOSFET device has an ultra-shallow junction under the first spacer to reduce the source/drain resistance and increase the operating rate of the device.

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Taichung Hsien, Taiwan

Kun-Cho Chen