Kabushiki Kaisha Toshiba

Kumiko Nomura

Takao Marukame

Yoshifumi Nishi

Shinobu Fujita

Keiko Abe

Koichi Mizushima

Hiroki Noguchi

Kazutaka Ikegami

Shinichi Yasuda

Tetsufumi Tanamoto

Masato Oda

Susumu Takeda

Radu Berdan

A synaptic circuit according to an embodiment is a circuit in which a weight value changed by learning is set. The synaptic circuit receives a binary input signal from a pre-synaptic neuron circuit and outputs an output signal to a post-synaptic neuron circuit. The synaptic circuit includes a propagation circuit and a control circuit. The propagation circuit supplies, to the post-synaptic neuron circuit, the output signal obtained by adding an influence of the weight value to the input signal. The control circuit stops output of the output signal from the propagation circuit to the post-synaptic neuron circuit when the weight value is smaller than a predetermined reference value.

Synaptic circuit and neural networking apparatus

A memory device according to an embodiment can be used for storing weights for a neural network. An update circuit changes a difference between charge amounts accumulated in first/second accumulation circuits in the memory device. An output circuit outputs, as a weight, a signal corresponding to the difference between the charge amounts. The update circuit performs the change of the difference by changing, when the update amount is positive, the electric charges accumulated in the first accumulation circuit in a first direction by a charge amount corresponding to an absolute value of the update amount, the first direction being either an increasing direction or a decreasing direction, and changing, when the update amount is negative, the electric charges accumulated in the second accumulation circuit in the first direction by a charge amount corresponding to an absolute value of the update amount.

Memory device and neural network apparatus

An arithmetic device includes N product-sum-operation circuits, a control circuit, and an output circuit. Each product-sum-operation circuit outputs intermediate signals obtained by binarizing a product-sum-operation value obtained by product-sum-operation of M input values of M input signals and M weight values. The control circuit inverts positive/negative of each M weight value at determining-timing when a given time elapses from input timing. Based on a delay time from the determination-timing to logic finalization of the intermediate signal for each N product-sum-operation circuit, the output circuit outputs an output signal representing a winner-product-sum-operation circuit for which the product-sum-operation value having a sign and the largest absolute value is calculated. Each N product-sum-operation circuit starts the product-sum-operation from the input-timing and the determination-timing, and outputs an intermediate signal for which a propagation-delay-time from starting of the product-sum-operation to inversion of the logic corresponds to the absolute value of the product-sum-operation value.

Arithmetic device and neural network device

A synaptic circuit according to an embodiment includes: a weight current circuit that applies a weight current corresponding to a weight value; an input switch that switches whether or not to cause the weight current circuit to apply the weight current; a capacitor that includes a first terminal and a second terminal, the first terminal being given a constant voltage; an output circuit that outputs the output signal corresponding to a capacitor voltage; a charge adjustment circuit that decreases or increases charges accumulated in the capacitor by drawing, from the second terminal, a capacitor current corresponding to a current value of the weight current, or supplying the capacitor current to the second terminal; and a control circuit that switches whether or not to reduce a current having a predetermined current value from the capacitor current in accordance with the weight value.

Synaptic circuit and neural network apparatus

According to an embodiment, an inference system includes a recurrent neural network circuit, an inference neural network, and a control circuit. The recurrent neural network circuit receives M input signals and outputs N intermediate signals, where M is an integer of 2 or more and N is an integer of 2 or more. The inference neural network circuit receives the N intermediate signals and outputs L output signals, where L is an integer of 2 or more. The control circuit adjusts a plurality of coefficients that are set to the recurrent neural network circuit and adjusts a plurality of coefficients that are set to the inference neural network circuit. The control circuit adjusts the coefficients set to the recurrent neural network circuit according to a total delay time period from timing for applying the M input signals until timing for firing the L output signals.

Processing apparatus and inference system

In a gate electrode of a nonvolatile memory device of an embodiment, a tunnel insulating film covers a channel region. A first current collector file is disposed on the side opposite to the channel region with respect to the tunnel insulating film. An ion conductor film is disposed between the tunnel insulating film and the first current collector film. A first electrode film is disposed between the tunnel insulating film and the ion conductor film. The first electrode film is in contact with the ion conductor film. A second electrode film is disposed between the ion conductor film and the first current collector film. The second electrode film is in contact with the ion conductor film. A second current collector film is disposed between the tunnel insulating film and the second electrode film.

Nonvolatile memory device

According to an embodiment, an operation apparatus includes a first neural network, a second neural network, an evaluation circuit, and a coefficient-updating circuit. The first neural network performs an operation in a first mode. The second neural network performs an operation in a second mode and has a same layer structure as the first neural network. The evaluation circuit evaluates an error of the operation of the first neural network in the first mode and evaluates an error of the operation of the second neural network in the second mode. The coefficient-updating circuit updates, in the first mode, coefficients set for the second neural network based on an evaluating result of the error of the operation of the first neural network, and updates, in the second mode, coefficients set for the first neural network based on an evaluating result of the error of the operation of the second neural network.

Operation apparatus

According to an embodiment, a synapse circuit includes: a buffer that changes an output signal to a second logical value at a timing when an input signal exceeds a first threshold level, in a case where the output signal has a first logical value in a first mode, and changes the output signal to the second logical value at a timing when the input signal exceeds a reference level lower than the first threshold level, in a case where the output signal has the first logical value in a second mode; an adjusting unit that adjusts the first threshold level depending on a stored coefficient; and a mode switching unit that operates the buffer in the first mode during a period in which an acquired spike is not generated, and operates the buffer in the second mode during a period in which the spike is generated.

Synapse circuit and arithmetic device

A spiking neural network device according to an embodiment includes a synaptic element, a neuron circuit, a synaptic potentiator, and a synaptic depressor. The synaptic element has a variable weight. The neuron circuit inputs a spike voltage having a magnitude adjusted in accordance with the weight of the synaptic element via the synaptic element, and fires when a predetermined condition is satisfied. The synaptic potentiator performs a potentiating operation for potentiating the weight of the synaptic element depending on input timing of the spike voltage and firing timing of the neuron circuit. The synaptic depressor performs a depression operation for depressing the weight of the synaptic element in accordance with a schedule independent from the input timing of the spike voltage and the firing timing of the neuron circuit.

Spiking neural net work device and learning method of spiking neural network device

According to an embodiment, a neural network apparatus includes cores, routers, a tree path, and a short-cut path. The cores are provided according to leaves in a tree structure, each core serving as a circuit that performs calculation or processing for part of elements of the neural network. The routers are provided according to nodes other than the leaves in the tree structure. The tree path connects the cores and the routers such that data is transferred along the tree structure. The short-cut path connects part of the routers such that data is transferred on a route differing from the tree path. The routers transmit data output from each core to any of the cores serving as a transmission destination on one of routes in the tree path and the short-cut path such that the calculation or the processing is performed according to a structure of the neural network.

Neural network apparatus

According to an embodiment, a neural network apparatus includes a plurality of neuron circuits, each including an integration circuit, a firing circuit, and a secondary battery. The integration circuit is configured to output an integral signal obtained by integrating input signals. The firing circuit is configured to generate, in accordance with the integral signal, a pulse signal to be transmitted to the neuron circuit provided at a subsequent layer. The secondary battery is configured to supply the firing circuit with drive electric power used for generating the pulse signal.

According to an embodiment, a reinforcement learning system includes a memristor array in which each of a plurality of first direction lines corresponds to one of a plurality of states, and each of a plurality of second direction lines corresponds to one of a plurality of actions, a first voltage application unit that individually applies voltage to the first direction lines, a second voltage application unit that individually applies voltage to the second direction lines, a action decision circuit that decides action to be selected by an agent in a state corresponding to a first direction line to which a readout voltage is applied, a action storage unit that stores action selected by the agent in each state that can be caused in an environment, and a trace storage unit that stores a time at which the state is caused by action selected by the agent.

Reinforcement learning system

According to an embodiment, an arithmetic device includes a comparator, M cross switches, and M coefficient circuits. The comparator compares a first voltage generated at a first comparison terminal and a second voltage generated at a second comparison terminal. The M cross switches are provided corresponding to the M input signals. The M coefficient circuits are provided corresponding to the M coefficients, and each includes a first constant current source and a second constant current source. Each of the M cross switches performs switching between a straight state and a reverse state. In each of the M coefficient circuits, the first constant current source is connected between a positive output terminal of the corresponding coefficient circuit and a reference potential, and the second constant current source is connected between a negative output terminal of the corresponding coefficient circuit and the reference potential.

Arithmetic device

According to an embodiment, a neural network device includes a plurality of cores, and a plurality of routers. Each of the plurality of routers includes an input circuit and an output circuit. Each of the plurality of cores transmits at least one of forward direction data propagating in the neural network in a forward direction and reverse direction data propagating in the neural network in a reverse direction. The input circuit receives the forward direction data and the reverse direction data from any one of the plurality of cores and the plurality of routers. The output circuit or the input circuit selectively deletes the reverse direction data stored based on a request signal for requesting reception of data.

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Tokyo, Japan

Kumiko Nomura