Cadence Design Systems, Inc.

Kumar Venkatramani

Wuudiann Ke

Merrill Hunt

Grant Edmund Martin

Henry C Chang

Christopher K Lennard

Khoan Truong

Larry Cooke

Peter Paterson

Laurence Hager Cooke

Jin-Sheng Shyr

Techniques for increasing flexibility in use of virtual component blocks include a method for hardening a foundation block, a pin-unscrambling methodology for semi-hardened virtual component blocks, and parameterizable virtual component blocks. A method for hardening a foundation block and utilizing it in a circuit design comprises the steps of defining a virtual component foundation block, hardening an interior region of the foundation block including at least the critical timing components such as the system bus. The foundation block has a 'soft collar' for allowing interface parameters to be specified when the foundation block is incorporated into a circuit design. In addition, the foundation block may comprise an internal, hierarchical clocking scheme for even clock distribution and optimum performance. For example, all internal clock delays may be padded, except the longest one, so that the clock signal arrives at all relevant reference points within the foundation block at the same time.

Adaptable circuit blocks for use in multi-block chip design

A method for designing a circuit block includes the steps of selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, at least one of said circuit blocks being programmable; collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method; accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk; upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks (FEA); and, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, in compliance with the criteria and modified constraints without changing the selected circuit block and the processing method.

Block based design methodology with programmable components

A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

Blocked based design methodology

Block based design methodology

A technique for constructing a balanced H-Tree clock layout suited for application to clock signals in integrated circuits, but applicable to other signals requiring balanced distribution over a wide area, involves routing clock wires in a circuit design wherein internal circuit blocks are divided, to the extent possible, into groups having an equal number of circuit blocks. An upper H-Tree clock layout structure is established using the center of mass of each of the circuit block groups as guideposts. Adjustments in wire length to balance the wires of the H-Tree layout. A lower H-Tree clock layout structure is established using center points between pairs of adjacent or nearby circuit blocks as guideposts for the endpoints of clock wires, and then routing, to the extent necessary, wire segments to the individual circuit blocks.

System and method for H-Tree clocking layout

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Saratoga, CA, United States of America

Kumar Venkatramani