Cadence Design Systems, Inc.

Kumar Subramani

Radu Zlatanovici

A double edge triggered circuit includes a clock gater responsive to a clock signal and an enable signal to output a gated clock signal, a first double edge triggered flip-flop that launches a data signal in response to the gated clock signal, and a second double edge triggered flip-flop that captures the data signal in response to the clock signal, wherein the clock gater stops the gated clock signal at a first logic value when the enable signal is at a first logic state, and the clock gater switches the gated clock signal from the first logic value at a next clock edge when the enable signal is at a second logic state.

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Redwood City, CA, United States of America

Kumar Subramani