Motorola Corporation

Kumar Shiralagi

Raymond K Tsui

Herbert Goronkin

Saied N Tehrani

Vijay K Nair

George N Maracas

Jenn-Hwa Huang

Sung P Pack

Richard W Mauntel

Christine Thero

Danny L Thompson

Nada El-Zein

Ruth Y Zhang

A sparse-carrier device including a crystal structure ( ) formed of a first material and having a crystallographic facet ( ) with a width (w) and a length and quantum dots ( ) formed of a second material and positioned in at least one row on the crystallographic facet ( ). The at least one row of quantum dots ( ) extends along the length of the crystallographic facet ( ) and is at least one quantum dot ( ) wide (w) and a plurality of quantum dots long. The number of quantum dot rows determined by the width (w) of the crystallographic facet ( ). The row of quantum dots ( ) form a building block for circuits based on sparse or single electron devices.

Sparse-carrier devices and method of fabrication

A sparse-carrier device comprising a crystal structure formed of a first material and including a crystallographic facet having a length, a first width and a second width, and quantum dots formed of a second material and positioned on the crystallographic facet, the quantum dots extending along the length of the crystallographic facet in a first distribution pattern along the first width and a second distribution pattern along the second width.

Quantum deposition distribution control

A sparse-carrier device includes a crystal structure with a crystallographic facet having contacts at opposite ends. Quantum dots are formed in first and second rows on the facet approximately one quantum dot wide and a plurality of quantum dots long, the quantum dots in the first row being separated from each other by a first distance smaller than a second distance between the quantum dots in the first row and adjacent quantum dots in a second row. The first distance is small enough to allow carrier tunneling between adjacent quantum dots and the second distance is large enough to substantially prevent tunneling between adjacent quantum dots and small enough to allow Coulombic interaction between adjacent quantum dots. Electrical contacts are formed at opposite ends of the rows to allow tunneling of carriers into and out of quantum dots in the first and second rows.

An ohmic contact including a gallium arsenide substrate having an epitaxially grown crystalline layer of indium arsenide on the substrate. The crystalline material and the substrate define an interface, layers are n-doped with silicon close to the interface.

Silicon delta-doped gallium arsenide/indium arsenide heterojunction OHMIC contact

A method of depositing a material to a semiconductor device having a first mesa structure, a second mesa structure and a valley. Material is deposited from a first angular direction sufficient to substantially mask the valley with a first of the mesa structures and from a second angular direction sufficient to substantially mask the valley with the second mesa structure to form a first lip and a second lip on the respective first and second mesa structures overlying the valley and defining a space therebetween less than the width of the valley. Material is then deposited to the device from a third direction in substantial opposition to the device, the space operating to guide material deposition to the valley to provide discrete material deposition in the valley to form a discrete feature in the valley.

Resistless device fabrication method

A method of improving contact resistance in a multi-layer heterostructure comprising the steps of providing a substrate, growing a crystalline material on the substrate, and doping close to an interface of the substrate and the crystalline material with n-silicon to provide continuity at the interface.

Ohmic contact and method of manufacture

A method of selective metallization/deposition including patterning a mask on the surface of a substrate structure to define contact areas, and utilizing a compound, including a metal, which dissociates under predetermined conditions. The dissociation and application of the predetermined conditions occurring either during deposition or after deposition to selectively form a layer of the metal on the contact areas.

Selective metallization/deposition for semiconductor devices

A method of fabricating ultra-small semiconductor devices including providing a mesa on a substrate. A plurality of overlying layers of semiconductor material are grown in overlying relationship to the mesa so that a perpendicular discontinuity is produced in the layers at the mesa sidewall and the first layer overlying the mesa is in contact with the last layer overlying the substrate adjacent the mesa. A spacer of nonconductive material is formed on the discontinuity and the plurality of overlying layers are etched, using the spacer as a mask, so as to form a contact area overlying the mesa and a contact area overlying the substrate adjacent the mesa, and a semiconductor device positioned adjacent the sidewall beneath the spacer and between the contact areas.

Methods of fabricating and contacting ultra-small semiconductor devices

A method of fabricating 3D semiconductor circuits including providing a conductive layer with doped polysilicon thereon patterned and annealed to form first single grain polysilicon terminals of semiconductor devices. Insulated gate contacts are spaced vertically from the terminals so as to define vertical vias and polysilicon is deposited in the vias to form conduction channels. An upper portion of the polysilicon in the vias is doped to form second terminals for the semiconductor devices, and the polysilicon is annealed to convert it to single grain polysilicon. A second electrically conductive layer is deposited and patterned on the second terminal to define second terminal contacts of the semiconductor devices.

Method of fabricating 3D multilayer semiconductor circuits

A VCO includes a transistor having a plurality of negative differential resistance devices coupled in series to the source terminal of the transistor, with each of the devices having a negative differential resistance operating region. Biasing circuits are coupled to the drain and gate terminals along with operating voltages which set the oscillator to operating in a negative differential resistance region of at least one of the negative differential resistance devices so that oscillations of a selected frequency are produced at an output terminal. The transistor, the plurality of N devices, the DC biasing circuits, and the operating voltages are connected so that the oscillator negative differential resistance operating region is greater than N times as wide as each of the device negative differential operating regions individually.

VCO with multiple negative differential resistance devices

A method of ion implanting a substrate is disclosed, which includes providing a substrate having a surface. A sacrificial layer of semiconductor material is formed on the surface and resistlessly patterning to define masked and unmasked portions. The unmasked portions are etched away to form an implantation mask on the substrate. Ions are implanted in the substrate underlying the etched away unmasked portions and the sacrificial layer is removed.

Method of resistless patterning of a substrate for implantation

A method of resistless gate metal etch in the formation of a field effect transistor is disclosed, which includes providing a first layer of a first semiconductor material having a surface. A second layer of a second semiconductor material is formed on the surface and resistlessly patterned to define a masked and an unmasked portions. The unmasked portion of the second layer is etched away to the first layer to enable gate formation.

Method of resistless gate metal etch for fets

A method of removing an oxide mask during fabrication of semiconductor devices which includes providing a providing a III-V compound semiconductor substrate having a surface, the surface having a growth area and a masked area masked by an oxide film formed on the surface thereof. The oxide film is removed with a Trisdimethylamino group V compound.

Masking methods during semiconductor device fabrication

A method of forming a mask including providing a fluid from a group including oxygen based, nitrogen based, or carbon based fluids, introducing a substrate of semiconductor material into the fluid, and growing a film with thickness in a range of 10-20 .ANG. on a surface by converting the fluid adjacent the surface into a reactive species. The reactive species is created by directing light having a wavelength at the absorption peak of the fluid so as to convert the fluid into the reactive species. The surface of the substrate reacts with the reactive species to form the film.

Masking methods for semiconductor materials

A method of masking a substrate to leave an exposed facet for processing during fabrication of a semiconductor devices including providing a substrate formed of a semiconductor material and having a structure projecting therefrom, the structure including a facet. Ultraviolet light is selectively directing onto the substrate at an angle to the structure and opposite the facet so that the structure shades the facet from the ultra violet light. The ultra violet light reacts with the material to form an oxide mask on the substrate leaving the facet unmasked.

Growing community of inventors

Chandler, AZ, United States of America

Kumar Shiralagi