Xilinx, Inc.

Advanced Micro Devices Corporation

Amazon Technologies, Inc.

Kumar Rahul

Santosh Yachareni

John J Wuu

Mahendrakumar Gunasekaran

Sriram Sethuraman

Weiguang Lu

Nui Chong

Pierre Maillard

Subodh Kumar

Uma E Durairajan

Karthy Rajasekharan

Michelle Zeng

Cheang Whang Chang

Md Nadeem Iqbal

Teja Masina

Mohammad Anees

Amarnath Perla

Sri Deepti Pisipati

Jitendra Kumar Yadav

Mrinmoy Goswami

Tabrez Alam

Md Hussain

Sanat Kumar Dubey

Sourabh Swarnkar

Gokul Puthenpurayil Ravindran

Suresh Babu Kotha

Disclosed are various embodiments for detecting potential quality issues in encoded video content. Frame level metrics included in metric data that is associated with an encoded video can be analyzed and one or more quality scores can be calculated using the frame level metric values. If the quality scores meet or exceed one or more threshold values, an alarm notification can be generated that identifies a video segment that has a quality issue along with the one or more quality scores. The alarm notification can be sent to an entity for further evaluation of the encoded video.

Detecting quality issues in encoded video

Embodiments herein describe a circuit for detecting a single event upset (SEU). The circuit includes a latch including an output node, a first parity node, and a second parity node and correction circuitry configured to correct a single event upset (SEU) at the output node using the first and second parity nodes.

System and method for SEU detection and correction

An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.

ECC optimization

An integrated circuitry (IC) device for a memory device includes driver circuitry, selection circuitry, clock generation circuitry, and self-time path circuitry. The driver circuitry generates a plurality of driver circuitry outputs. The selection circuitry selects one of the plurality of driver circuitry outputs based on a plurality of enable signals. The clock generation circuitry receives the selected one of the plurality of driver circuitry outputs from the selection circuitry, and generates a clock signal based on at least the selected one of the plurality of driver circuitry outputs from the selection circuitry. The self-time path circuitry of a memory receives the clock signal and generates a reset signal based on the clock signal. The plurality of driver circuitry outputs and the clock signal are based on the reset signal, and the self-time path circuitry corresponds to one or more columns of a memory bank.

Single port memory with multiple memory operations per clock cycle

A memory device is disclosed herein that leverages high ratio column MUXES to improve SEU resistance. The memory device may be utilized in an integrated circuit die and chip packages having the same. In one example, as semiconductor memory device is provided that includes first and second arrays of semiconductor memory cells, a plurality of sense amplifiers configured to read data states from the first and second arrays of memory cells, and a first plurality of high ratio MUXES connecting the first and second arrays of memory cells to the plurality of sense amplifiers.

Single event upset tolerant memory device

Examples described herein generally relate to devices that include a pulsed flip-flop capable of being implemented across multiple voltage domains. In an example, a device includes a pulsed flip-flop. The pulsed flip-flop includes a master circuit and a slave circuit sequentially connected to the master circuit. The master circuit includes a pre-charge input circuit and a first latch. A first node is connected between the pre-charge input circuit and the first latch. The slave circuit includes a resolving circuit and a second latch. The first node is connected to an input node of the resolving circuit. A second node is connected between the resolving circuit and the second latch. The resolving circuit is configured to selectively (i) pull up or pull down a voltage of the second node and (ii) be disabled.

Pulsed flip-flop capable of being implemented across multiple voltage domains

A circuit includes a master latch circuit and a slave latch circuit. The master latch circuit is configured to receive an input data signal associated with an input data voltage domain and generate a first output data signal associated with an output data voltage domain different from the input data voltage domain. The slave latch circuit is configured to receive, from the master latch circuit, the first output data signal and generate a second output data associated with the output data voltage domain.

Method and apparatus for multi-voltage domain sequential elements

An integrated circuit (IC) includes an encoder circuit configured to receive input data including a plurality of data bits. A plurality of parity computation equations for a single error correct double error detect adjacent double error correct adjacent triple error detect (SECDEDADECADTED) Hamming code is received. A plurality of parity bits are computed using the plurality of parity computation equations. Write data including the data bits and the parity bits are provided to a write circuit. The write circuit writes the write data to a memory.

Method and apparatus for error detection and correction

An apparatus includes an encoder circuit block configured to receive input data. The encoder circuit block is configured to generate a plurality of parity bits from the input data and order the input data and the plurality of parity bits to generate encoded data. The encoder circuit block is configured to generate each of the plurality of parity bits based upon selected bits of the input data and orders the input data and the plurality of parity bits so that a decoder circuit block configured to decode the encoded data is able to perform operations including, at least in part, detecting a no bit error, detecting and correcting a single bit error, detecting a double bit error, detecting and correcting an adjacent double bit error, and detecting an adjacent triple bit error. The operations are independent of a number of memory banks used to store the encoded data. The decoder circuit block may also correct an adjacent triple bit error.

Encoding and decoding information for detecting and correcting bit errors

An integrated circuit (IC) includes an encoder configured to receive input data including a plurality of data bits. The encoder includes a parity computation matrix circuit configured to arrange the data bits according to a matrix format to generate a parity computation matrix. A parity computation circuit is configured to compute a plurality of parity computation row terms corresponding to rows of the parity computation matrix respectively, compute a plurality of parity computation column terms corresponding to columns of the parity computation matrix respectively, and compute parity bits using the parity computation row terms and parity computation column terms. Write data including the data bits and the parity bits are provided to a write circuit. The write circuit writes the write data to a memory cell array in a memory.

In an example, a memory circuit in a programmable integrated circuit (IC) includes: a control port and a clock port; a configurable random access memory (RAM) having a control input and a clock input; input multiplexer logic coupled to the control input and the clock input; and a state machine coupled to the input multiplexer logic and configuration logic of the programmable IC, the state machine configured to: in response to being enabled by the configuration logic, control the input multiplexer logic to switch a connection of the control input from the control port to the state machine and, subsequently, switch a connection of the clock input from the clock port to a configuration clock source; and in response to being disabled by the configuration logic, control the input multiplexer logic to switch the connection of the clock input from the configuration clock source to the clock port and, subsequently, switch the connection of the control input from the state machine to the control port.

Implementing robust readback capture in a programmable integrated circuit

An embodiment of an apparatus for encoding. For this embodiment of the apparatus, an encoder block is coupled to receive input data. The encoder block has an R-matrix block. The R-matrix block is configured to: exclusively OR combinations of subsets of data bits of the input data to generate (n&#x2212;1) parity bits for n a positive integer greater than zero; and exclusively OR a combination of all of the data bits and all the (n&#x2212;1) parity bits to generate an (n) parity bit 9-to-7.

Encoding and decoding of information using a block code matrix

An encoder block to receive input data has a KR-Matrix block. The KR-Matrix block is configured to: exclusively OR combinations of subsets of data bits of the input data to generate (n&#x2212;1) parity bits for n a positive integer greater than zero; and exclusively OR a combination of all of the data bits and all the (n&#x2212;1) parity bits to generate an (n) parity bit.

Growing community of inventors

Hyderabad Telangana, India

Kumar Rahul