Qualcomm Incorporated

Kumar Kanti Ghosh

Matthew Levi Severson

Christopher Kong Yee Chun

Dipti Ranjan Pal

Joshua Stubbs

Sravan Kumar Ambapuram

Venkata Biswanath Devarasetty

Nirav Narendra Desai

Sharath Kumar Nagilla

Prashanth Kumar Kakkireni

Venkatesh Ravipati

Chandan Agarwalla

Lakshmi Narayana Panuku

Shrikanth Shenoy

Nilanjan Banerjee

Shishir Joshi

Various embodiments may include methods and systems for power management of multiple chiplets within a system-on-a-chip (SoC). Various systems may include a power management integrated circuit (PMIC) configured to supply power to a first chiplet and a second chiplet across a shared power rail. The first chiplet may be configured to obtain first sensory information throughout the first chiplet. The second chiplet may be configured to obtain second sensory information throughout the second chiplet, and may be configured to transmit a voltage change message to the first chiplet based on the second sensory information. The first chiplet may be configured to transmit a power rail adjustment message to the PMIC based on the first sensory information and the voltage change message. The PMIC may be configured to adjust the voltage of at least one of the first chiplet and the second chiplet.

Power management for multiple-chiplet systems

Dynamic power supply voltage adjustment in a computing device may involve two stages. In a first stage, a first method for adjusting a power supply voltage may be disabled. While the first method remains disabled, a request to adjust the power supply voltage from an initial value to a target value using a second method may be received. The second method may be initiated in response to the request if a time interval has elapsed since a previous request to adjust the power supply voltage. In a second stage, the first method may be enabled when it has been determined that the power supply voltage has reached the target value.

Two-stage dynamic power supply voltage adjustment

An apparatus sets an operating voltage of a shared power rail in a multi-core electronic device. The apparatus includes a system-on-chip (SoC) having multiple cores with each core in the SoC configured to report an operating status. The apparatus includes an operating state aggregator configured to receive the operating status reported from each core in the SoC and to select the selected operating voltage based on the operating status from each core. A voltage regulator is in communication with the operating state aggregator and a power management integrated circuit (PMIC). The selected operating voltage is then programmed into the (PMIC) to control the shared power rail.

Dynamic voltage selection for a single power rail in a multi-core domain

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San Diego, CA, United States of America

Kumar Kanti Ghosh