Freescale Semiconductor,inc.

International Business Machines Corporation

Qualcomm Incorporated

Qualcomm Atheros Inc.

Kumar K Gala

Gary L Whisenhunt

Michael D Snyder

Bryan D Marietta

David B Kramer

Becky Bruce

Harlan Titus Beverly

Giles R Frazier

Bradly George Frey

Cathy May

James Xenidis

Sanjay Raghunath Deshpande

Charles A Musta

A method and circuit for a data processing system () provide a processor-based partitioned priority blocking mechanism by storing priority levels and associated partition information in special purpose registers (-) located at the processor core () to enable quick and efficient interrupt priority blocking on a partition basis.

Interrupt priority management using partition-based priority blocking processor registers

A method and circuit for a data processing system () provide a processor-based partitioned priority blocking mechanism by storing interrupt identifiers, partition identifiers, thread identifiers, and priority levels associated with accepted interrupt requests in special purpose registers (-) located at the processor core () to enable quick and efficient interrupt priority blocking on a partition basis.

Processor interrupt interface with interrupt partitioning and virtualization enhancements

A method and circuit for a data processing system provide virtualized instructions for accessing a partitioned device (e.g.,) by executing a control instruction () to encode and store an access command (CMD) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register () at a physical address (PA) retrieved from a special purpose register () so that the partitioned device () can determine if the access command can be performed based on local access control information.

Virtualized instruction extensions for system partitioning

A method and circuit for a data processing system provide a partitioned interrupt controller with an efficient deferral mechanism for processing partitioned interrupt requests by executing a control instruction to encode and store a delay command (e.g., DEFER or SUSPEND) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register () at a physical address (PA) retrieved from a special purpose register () so that the partitioned interrupt controller () can determine if the delay command can be performed based on local access control information.

Virtualized interrupt delay mechanism

A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled.

Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition

A method of communicating with a network interface includes providing a packet to the network interface, where the packet includes an address field indicating a destination of the packet. The network interface analyzes the address field, and determines if it reflects an address associated with the network interface. If not, the network interface provides the packet to a network. If the network interface determines the address field reflects an address associated with the interface, it provides information in the packet to an application executing at the network interface. Accordingly, information targeted to an application can be communicated by associating an address, such as a network address, with the network interface, allowing for communication of the information without extensive processing of each packet at the interface.

Method and system for communication between nodes

A method for receiving a first indication from a host device is comprised. The device is a first port of the host device that has been reserved fro a network device. The method also poses as the host device at the network device in response to a receipt of the first indication.

Intermediate network device for host-client communication

Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition

A method is disclosed that receives a function call at an application program interface. The method selects a first processor of a plurality of processors to execute the function call. The method further executes a first transmit function associated with a bus coupled to the first processor. The first transmit function includes a function parameter associated with the function call.

Distributed processing system and method

A method includes communicating a first message between processors of a multiprocessor system via a coherency interconnect, whereby the first message includes coherency information. The method further includes communicating a second message between processors of the multiprocessor system via the coherency interconnect, whereby the second message includes interprocessor message information. A system includes a coherency interconnect and a processor. The processor includes an interface configured to receive messages from the coherency interconnect, each message including one of coherency information or interprocessor message information. The processor further includes a coherency management module configured to process coherency information obtained from at least one of the messages and an interrupt controller configured to generate an interrupt based on interprocessor message information obtained from at least one of the messages.

Interprocessor message transmission via coherency-based interconnect

A processing device includes a first storage location configured to store a first value associated with a first address space, a second storage location configured to store a second value associated with a second address space, and a third storage location configured to store a third value associated with a third address space. The processing device further includes a memory management unit, which includes a first input configured to receive a first address value associated with a data transfer operation, a second input configured to receive an identifier associated with the data transfer operation, and an address space select module configured to identify a select value from the first value, the second value and the third value based on the identifier. The memory management module further includes an address modification module configured to generate a second address value based on the first address value and the select value.

Growing community of inventors

Austin, TX, United States of America

Kumar K Gala