Virident Systems, Inc.

Intel Corporation

Vxtel, Inc.

Kumar Ganapathy

Vijay Karamcheti

Kenneth Alan Okin

Rajesh Parekh

Ashish Singhai

Ruban Kanapathipillai

Ruban Kanapathippillai

George Moussa

Earle F Philhower, Iii

Saurin Shah

Ruchir Shah

Kenneth Malich

Thu Nguyen

Manoj Mehta

Siva Venkatraman

Hooman Honary

Siva Simanapalli

Amit R Gupta

Ruban Kanapathipiillai

An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.

Apparatus with a memory controller configured to control access to randomly accessible non-volatile memory

In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.

Network computer systems with power management

A read writeable random accessible non-volatile memory module includes a printed circuit board with an edge connector that can be plugged into a socket of a printed circuit board. The read writeable random accessible non-volatile memory modules further include a plurality of read writable non-volatile memory devices.

Read writeable randomly accessible non-volatile memory modules

A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.

Seamless application access to hybrid main memory

A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.

Methods of communicating to different types of memory modules in a memory channel

Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.

Asymmetric memory migration in hybrid main memory

Memory channel connected non-volatile memory

A memory module is provided. In one example, the memory module includes a printed circuit board with one or more connectors, and a plurality of multi-chip packaged integrated circuit parts mounted to the printed circuit board. Each of the plurality of multi-chip packaged integrated circuit parts includes an integrated circuit package including a slave memory controller (SMC) die and one or more pairs of (1) a spacer under the slave memory controller die and (2) a flash memory die under the spacer. Each flash memory die is larger than each spacer to provide an opening into a perimeter of the flash memory die to which electrical connections may be made.

Memory modules with multi-chip packaged integrated circuits having flash memory

Methods of managing power in network computer systems

In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.

Methods for accessing memory in a two-dimensional main memory having a plurality of memory slices

In one embodiment of the invention, a method of upgrading main memory in a computer system is disclosed. The method includes plugging a plurality of two dimensional memory modules into a plurality of memory module sockets and coupling a master memory controller between one or more processors and the plurality of memory modules. Each of the two dimensional memory modules includes memory in a plurality of memory slices and a plurality of slave memory controllers respectively coupled to the memory in the plurality of memory slices. According, the upgrading method further includes buffering and transposing data between a column by column format for the one or more processors and a row by row format for the memory in the plurality of memory slices.

Methods for upgrading main memory in computer systems to two-dimensional memory modules and master memory controllers

Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component.

Integrating data from symmetric and asymmetric memory

A multi-chip packaged integrated circuit part for mounting to a printed circuit board of a memory module. The multi-chip packaged integrated circuit part comprises an integrated circuit package including a slave memory controller (SMC) die; and pairs of a spacer under the slave memory controller die, and a flash memory die under the spacer. In each pair, the flash memory die may be larger than the spacer so that an opening is provided into a perimeter of the flash memory die to allow electrical connections to be made. A plurality of conductors may be used to electrically couple the slave memory controller die and the flash memory die to one or more pads of a pin-out of the integrated circuit package.

Growing community of inventors

Los Altos, CA, United States of America

Kumar Ganapathy