Xilinx, Inc.

Kumar Deepak

Hem C Neema

Sonal Santan

Jason Villarreal

Valeria Mihalache

Jimmy Zhenming Wang

David K Liddell

Saikat Bandyopadhyay

Paul R Schumacher

Nabeel Shirazi

Roger Ng

Wei Lin

L James Hwang

Chi Bun Chan

Amitava Majumdar

Sandeep S Deshpande

Ishita Ghosh

Sushama Ghanekar

Georgios Tzimpragos

Roger Brent Milne

Xiaoyong Liu

Ralph D Wittig

Sundararajarao Mohan

Jeffrey Stroomer

Christopher H Kingsley

Graham F Schelle

Pramod Chandraiah

Haibing Ma

Satish R Ganesan

Peter Frey

Mahesh Sankroj

Alain Darte

Singh Vinay Jitendra

Feng Cai

Nikhil A Dhume

Scott H Jonas

Jayashree Rangarajan

Radharamanan Radhakrishnan

Yuxiong Zhu

Disclosed approaches monitor states of a plurality of sets of a plurality of handshake signals. Each set of handshake signals is associated with a respective one sub-circuit of a plurality of sub-circuits. For each sub-circuit, a beginning of an iteration by the sub-circuit is detected based on states of the plurality of handshake signals of the set associated with the sub-circuit. A graphics object is generated in response to detecting the beginning of the iteration. The graphics object is displayed on a display device and overlaid on a timeline associated with the sub-circuit. The graphics object has a bound that corresponds to the beginning of the iteration. The end of the iteration is detected based on the states of the associated set of handshake signals, and the graphics object is bounded on the timeline to indicate the end of the iteration.

Method and system providing visualization of sub-circuit iterations based on handshake signals

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating transaction associations in a waveform display. One of the methods includes receiving data representing a main signal for a selected transaction in a waveform display, the main signal including a plurality of main signal events. A search is performed for data representing one or more side signals associated with the main signal for the selected transaction, each side signal including a plurality of side signal events representing other transactions that are associated with the main signal at a time indicated by a corresponding main signal event. A visual indication is generated within the waveform display of an association between the selected transaction and one or more transactions identified by the one or more side signals associated with the main signal for the selected transaction.

Transaction associations in waveform displays

An execution circuit inputs a plurality of data units, performs unit operations on the data units, and registers results of the unit operations in response to oscillations of a clock signal. A control circuit controls activation of the unit operations, and outputs a start signal to the execution circuit to activate each unit operation and/or a completion signal to indicate completion of each unit operation. A debug circuit stores breakpoint flags associated with the unit operations. Each breakpoint flag has a state that specifies whether to stop oscillations of the clock signal. The debug circuit further receives the start and/or completion signal and evaluates, while the clock signal oscillates to the execution circuit, a state of the start and/or completion signal and a state of the breakpoint flag associated with the unit operation. Oscillations of the clock signal are stopped in response to the evaluation of the signals.

Breakpointing circuitry that evaluates breakpoint conditions while running clock to target circuit

Tracing operation of a kernel can include comparing, using a processor, signals of a compiled kernel with a database including compiler generated signals for compute units to determine a list of the signals of the compiled kernel that match the compiler generated signals and generating trace data by emulating the compiled kernel using the processor. The trace data includes values for signals of the compiled kernel collected over time during the emulation. Operational data corresponding to individual compute units of the compiled kernel can be determined from values of the signals of the list within the trace data using the processor. The operational data can be displayed using the processor.

Kernel tracing for a heterogeneous computing platform and data mining

Simulating a hardware description language design including a core and a testbench can include performing, using a processor, a first compilation of the hardware description language design by generating a compiled core unit for the core, a compiled testbench for the testbench, and synchronization data describing signals crossing a compile checkpoint boundary. A subsequent compilation of the hardware description language design can be performed by reusing the compiled core unit from the first compilation and generating a new compiled testbench for the testbench using the synchronization data.

Framework for reusing cores in simulation

An execution circuit is configured to input data units, perform unit operations on the data units, and register results of the unit operations in response to oscillations of a clock signal. A control circuit controls activation and deactivation of the unit operations. A debug circuit inputs, in parallel with input of the data units to the execution circuit, at least one of the data unit or one or more attributes associated with the data unit. The debug circuit evaluates, upon each input of the at least one of the data unit or the one or more attributes, a breakpoint condition based on the at least one of the data unit or the one or more attributes while the clock signal oscillates. In response to evaluation of the breakpoint condition indicating a break, the debug circuit stops oscillations of the clock signal to the execution circuit.

Data unit breakpointing circuits and methods

Simulating a circuit design can include detecting, using a processor, an assignment for a signal of a circuit design during a delta cycle of a simulation of the circuit design and comparing, using the processor, a range of the assignment for the signal with a range of an existing event for the signal for the delta cycle. In response to determining that the range of the assignment for the signal and the range of the existing event meet a condition, the existing event is updated, using the processor, resulting in a merged event. The merged event is scheduled for execution for the delta cycle using the processor.

Scheduling events in hardware design language simulation

Implementing a design for a heterogeneous computing platform can include storing, using a processor, profile data in a memory, wherein the profile data is generated from running the design for the heterogeneous computing platform and wherein the design includes a kernel adapted for hardware acceleration. Compliance of the design with a profile rule may be determined by comparing, using the processor, the profile data accessed from the memory with the profile rule. The profile rule can specify a design requirement for a hardware accelerated implementation of the kernel. Compliance of the design with the profile rule can be indicated, using the processor, based upon the comparing.

Implementation and evaluation of designs for heterogeneous computing platforms with hardware acceleration

For generating code for simulation of a circuit design, a hardware description language (HDL) description and a high-level language (HLL) description of portions of the circuit design are input. The HLL description specifies a first function and the HDL description includes a call to the first function. A wrapper is generated for the first function. The wrapper has an associated stack frame and includes code that stores in the stack frame values of arguments specified by the call to the first function and code that calls the first function. An HLL simulation specification is generated from the HDL description. The HLL simulation specification includes a call to the first HLL wrapper in place of the call to the first function. The HLL simulation specification, the first HLL wrapper, and the HLL description are compiled into executable program code.

Mixed-language simulation

Disclosed approaches for configuring a memory include generating by a high-level synthesis (HLS) tool executing on a computer system, a first mapping of elements of a high-level language (HLL) program to elements of a hardware language finite state machine that represents a circuit implementation of the HLL program. The HLS tool further generates a second mapping of lines of the HLL program to states of the hardware language finite state machine and stores the information describing the first mapping and the second mapping in a data structure of a database in the memory.

Debugging system and method

An approach for debugging a circuit implementation of a software specification includes translating a high-level language debugging command into a hardware debugging command that specifies the value(s) of a condition in the circuit implementation, and a storage element(s) at which the value(s) of the condition is stored. The hardware debugging command is transmitted to a debug controller circuit that generates a single clock pulse to the circuit implementation. The debug controller circuit reads a value(s) from the storage element(s) specified by the hardware debugging command and determines whether or not the value(s) satisfies the condition. The debug controller circuit generates another single clock pulse in response to the value(s) read from the storage element(s) not satisfying the condition. Generation of pulses of the clock signal is suspended and data indicative of a breakpoint is output in response to the value(s) read from the storage element(s) satisfying the condition.

Approaches for debugging include receiving by a hardware debug server, a high-level language (HLL) debugging command for setting a breakpoint in an HLL software specification. The hardware debug server translates the HLL debugging command into a hardware debugging command that specifies a condition of a hardware finite state machine that is representation of the software specification. The hardware debugging command is input to a simulator. The simulator adds a conditional breakpoint on the finite state machine in response to the hardware debugging command and executes a simulation of the finite state machine representation. Execution of the simulation is suspended in response to the detecting the condition in the finite state machine.

System and method for debugging software executed as a hardware simulation

A system may include a first region implemented in programmable circuitry of a programmable integrated circuit. The first region may include predefined interface circuitry configured to communicate with a host processor. The system may include a second region implemented in the programmable circuitry of the programmable integrated circuit. The second region may include a first hardware accelerated kernel of an OpenCL application. The system may include a first monitor circuit implemented within the first region or the second region. The first hardware accelerated kernel and the first monitor circuit may be coupled to the interface circuitry of the first region. The first monitor circuit may be operable responsive to control signals received from the host processor of a platform through the interface circuitry to store operation data for the first region or the first hardware accelerated kernel.

Device profiling for tuning OpenCL applications on programmable integrated circuits

A method for compiling an HDL specification for simulation of a circuit design is disclosed. The circuit design is elaborated from the HDL specification and memory locations are allocated for formals and actuals of the elaborated circuit design. For each port having a formal and an actual that are compatible, the allocating of memory locations sets a reference pointer for the formal and a reference pointer for the actual to reference a same one of the memory locations. For each port having a formal and an actual that are incompatible, the allocating of memory locations sets the reference pointer for the formal and the reference pointer for the actual to reference different respective ones of the memory locations. Simulation code modeling the elaborated circuit design is generated that updates a formal and actual of a port that are compatible using a single write operation to the referenced memory location.

Performance and memory efficient modeling of HDL ports for simulation

A method and apparatus for verifying and debugging a circuit design module of a high level programming system is disclosed herein. A circuit design created in a high level programming environment must undergo a number of transformations as it is compiled into a form that can be realized in hardware. At each transformative step, the behavior of the circuit must be verified with a simulation model and debugged if the transformation has changed the behavior of the circuit. The claimed invention presents a novel approach for verifying and debugging between different simulation models and achieves an advance in the art by utilizing the modularized structure of a high-level circuit design to systematically identify simulation mismatches among different simulation models and determine which portions of the circuit design are responsible for the discrepancy.

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San Jose, CA, United States of America

Kumar Deepak