Lsi Logic Corporation

Kumar Bhattaram

Daniel R Watkins

Venkat Mattela

Gagan V Gupta

Satish Venugopal

Kosala Abeywickrema

The present invention discloses a system to reverse-synthesize a gate level netlist definition of an integrated circuit (IC) design to corresponding register transfer level (RTL) definition of the same circuit. The typical process to implement an integrated circuit is to complete the RTL design first, which is then used, to generate gate level netlist definition, and eventually, a layout level design targeted to a particular process technology. The RTL design definitions, being a general description of the circuit, may be ported to different process technologies. However, the gate netlist level design, being a more specific or lower level definition of the circuit, is not easily ported to other integrated circuit design processes. To port a gate netlist level design to another process technology, the gate netlist should be converted, or reverse-synthesized back to a RTL level design. The present invention describes the method and apparatus to reverse-synthesize gate netlist level definitions into RTL definitions by parsing and analyzing the gate netlist level definition, generating an equivalent RTL definition, and verifying correctness of the RTL definition.

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Fremont, CA, United States of America

Kumar Bhattaram