Texas Instruments Corporation

Kumar Anurag Shrivastava

Subhashish Mukherjee

Sreeram Subramanyam Nasum

Madhulatha Bonu

Swaminathan Sankaran

Anant Shankar Kamath

Abhijit Anant Patki

Tarunvir Singh

Siraj Akhtar

Suvadip Banerjee

Somshubhra Paul

Kishalay Datta

Anoop Narayan Bhat

Robert Floyd Payne

Jeffrey Alan West

Mark Edward Wentroble

Rakesh Hariharan

Eleazar Walter Kenyon

Atul Singh

Sreeram N S

Arlo James Aude

Kashyap Jayendra Barot

Rr Manikandan

Niranjan Shankar

Kashyap Barot

Gurumurti Kailaschandra Avhad

Arushi Agrawal

An example apparatus includes: transmitter channel circuitry including: a buffer having an output; and a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the output of the buffer; an isolation transformer including: a first inductor having a terminal coupled to the second terminal of the capacitor; and a second inductor magnetically coupled to the first inductor across an isolation barrier, and receiver channel circuitry coupled to the second inductor.

Methods and apparatus for edge-triggered digital isolator circuitry

An example packaged IC includes a lead frame having a supply pin and a ground pin. The supply pin includes first and second supply leads extending from a proximal portion of the supply pin. The ground pin includes first and second ground leads extending from a proximal portion of the ground pin. A first IC network has a first supply terminal coupled to the first supply lead via a first conductor (e.g., bond wire or bump bond). The first IC network also has a first ground terminal coupled to the first ground lead via a second conductor. A second IC network has a second supply terminal coupled to the second supply lead via a third conductor. The second IC network also has a second ground terminal coupled to the second ground lead via a fourth conductor.

Integrated circuit package with star-connected lead

A circuit includes a switch and a switch controller. The switch has a first terminal coupled to a voltage supply terminal, a second terminal coupled to a ground terminal and to a first bondwire terminal. The switch controller includes: a first resistor, a second resistor, a capacitor, and a buffer circuit. The first resistor has a first terminal coupled to a second bondwire terminal. The second resistor has a first terminal coupled to the voltage supply terminal and has a second terminal coupled to a second terminal of the first resistor. The capacitor has a first terminal coupled to the ground terminal and to the first bondwire terminal and has a second terminal coupled to second terminals of the first and second resistors. The buffer circuit has a terminal coupled to the second terminal of the capacitor and has an output terminal coupled to the control terminal of the switch.

Integrated circuit with bondwire fault detection circuit

In some examples, an apparatus includes an isolating transformer and a grounding circuit. The isolating transformer has first and second coils separated by an isolation barrier, the first coil having first and second terminals. The grounding circuit is coupled to the first and second terminals. The grounding circuit is configured to couple the first and second terminals to a ground terminal during a first time period. The grounding circuit is also configured to decouple the first and second terminals from the ground terminal during a second time period.

Isolator circuit

An integrated semiconductor device having a metallic element formed between a capacitor with and a doped region.

Device isolators

An example apparatus includes: an on-off keying (OOK) modulator including: a first transistor including a first control terminal; a second transistor including a first current terminal, a second current terminal, and a second control terminal, the first current terminal coupled to the first control terminal; a third transistor including a third current terminal, a fourth current terminal, and a third control terminal, the third current terminal coupled to the first control terminal; a fourth transistor including a fifth current terminal, the fifth current terminal coupled to the second current terminal; and a fifth transistor including a sixth current terminal, the sixth current terminal coupled to the fourth current terminal.

Methods and apparatus to reduce variations for on-off keying transmissions

An example apparatus includes: a compensation circuit including: a current compensation output, a first transistor with a first current terminal and a first control terminal, the first current terminal coupled to the current compensation output, and a resistor ladder with a tap terminal coupled to the first control terminal, a current mirror circuit having a mirror input and a mirror output, the mirror input coupled to the current compensation output, and a rectification circuit having an input coupled to the mirror output.

Methods and apparatus to implement compensation circuitry in an envelope detector

In described examples, an integrated circuit includes an on-off keying (OOK) digital isolator, which includes a first circuitry, a multiplexer, an OOK modulator, an isolation barrier, an OOK envelope detector, and a second circuitry. The first circuitry generates and outputs a calibration signal. The multiplexer has a data signal input, and an input coupled to a first circuitry output. An OOK modulator input is coupled to a multiplexer output. An isolation barrier input is coupled to an OOK modulator output. An OOK envelope detector input is coupled to an isolation barrier output. The second circuitry includes an input coupled to an OOK envelope detector output, and an output coupled to an OOK envelope detector control input. The second circuitry detects a duty cycle distortion (DCD) of the OOK envelope detector output, and outputs a control signal to change the OOK envelope detector output's duty cycle based on the detected DCD.

Self-calibrating on-off keying based digital isolator

Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.

Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop

A digital isolator comprising a set of bipolar transistors and an inductor capacitor (LC) oscillator coupled to the set of bipolar transistors in series, wherein the LC oscillator is configured to be turned on and off based on the current applied to the set of bipolar transistors or the LC oscillator and generate a set of differential signals based on the current flowing through the set of bipolar transistors and mimicking the operational characteristics of an optocoupler.

Optocoupler emulating input stage for digital isolators

An encoding and transmitting system for a digital isolator system includes a transmitter for transmitting combined edge indicator signals through an isolation barrier, an encoder for generating the combined edge indicator signals based on first and second signals, a refresh clock generator for generating a refresh clock signal based on the first signal, and a refresh edge generator for masking at least a portion of the refresh clock signal, such that the portion of the refresh clock signal is not reflected in the second signal. The isolation barrier of the digital isolator system may be a capacitive isolation barrier for galvanically isolating a receiver from the transmitter. If desired, the refresh edge generator may include a refresh mask generator, one or more logic gates, and a glitch filter. A method of operating a digital isolator system is also described.

Architecture for resolution of data and refresh-path conflict for low-power digital isolator

Methods and apparatus generate an oscillating output signal having a voltage swing greater than a voltage swing across nodes of active devices. An example oscillator includes a tank to generate an oscillating output signal in response receiving an edge of an enable signal; a feedback generator including a first gain stage forming a first feedback loop with the tank, the first feedback loop providing a first charge to maintain the oscillating output signal and a second gain stage forming a second feedback loop with the tank, the second feedback loop providing a second charge to maintain the oscillating output signal, the first and second charges combining with the oscillating output signal to generate a high voltage swing; and an attenuator connected between the tank and the feedback generator to isolate the tank from active components of the feedback generator.

Oscillator apparatus

An oscillator for use in pulse communication of pulse signals with a startup latency and a pulse oscillation signal (such as for use in a transmitter for OOK pulse communication with pulse modulation). The oscillator includes an LC resonator having a tank impedance, and including a high-side node (Vp), and a low-side node Vn, and having a tank voltage corresponding to [Vp-Vn]. A pulse startup circuit, includes a PMOS transistor with a source connected to a supply voltage VDD, and a drain connected through a resistance R to the Vp node (where R is significantly larger than the tank impedance), and connected to an attenuation capacitance, in parallel with the resistance R. The PMOS control terminal is coupled to receive a kick start pulse to initiate a pulse signal. the oscillator can include high-side and low-side pulse startup circuits.

Oscillator for pulse communication with reduced startup latency

An IC includes a substrate including metal levels thereon including a top and bottom metal level with at least a transmit (Tx) circuit and receive (Rx) circuit each having &#x2265;1 isolation capacitor and an inductor. A scribe seal around the IC includes a first portion around the Tx circuit and second portion around the Rx circuit, utilizing &#x2265;2 of the metal levels including at least an outer metal stack. The Tx and Rx circuits are side-by-side along a direction that defines a length for the scribe seal. The outer metal stack includes a neck region between the scribe seal portions including a shorting structure including metal level(s) for shorting together the outer metal stack of the scribe seal portions. An optional routing pass-through isolated from the shorting structure includes other metal layers connecting through the neck region between node(s) within the first and second scribe seal portion.

Integrated circuit with inductors having electrically split scribe seal

An inductively coupled multi-channel digital isolator where the transmitter and receiver inductive loops of a given channel are coplanar. In the case where two adjacent channels flow data in opposite directions, the receiver inductive loops of a given channel include a large, generally conventional loop portion and a small loop portion that is located inside the transmitter inductive loops of the adjacent channels. The sizes of the small loop portion and the conventional loop portion are generally in the ratio of the magnetic flux in the conventional loop portion to the magnetic flux in the transmitter inductive loop. This size relationship results in the voltage of the small loop portion being very close but opposite in sign to the voltage in the conventional loop portion. As a result, there is minimal crosstalk from the transmitter inductive loop of one channel to the receiver inductive loop of the adjacent channel.

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Bengaluru, India

Kumar Anurag Shrivastava