Nxp Usa, Inc.

Freescale Semiconductor,inc.

Texas Instruments Corporation

Nxp B.v.

Kumar Abhishek

Srikanth Jagannathan

Sunny Gupta

Mukesh Bansal

Nitin Pant

Kushal Kamal

Garima Sharda

Samaksh Sinha

Hector Adrian Sanchez

Stefano Pietri

Thomas Henry Luedeke

Xiankun Jin

Prashant Bhargava

Sunny Arora

Shubhra Singh

Shilpa Gupta

Siddi Jai Prakash

Douglas Alan Garrity

Mohit Arora

Michael A Stockinger

Rakesh Pandey

Nihaar N Mahatme

Gaurav Goyal

Gayathri Bhagavatheeswaran

Pedro Barbosa Zanetta

Anurag Jindal

Manmohan Rana

Joseph Rollin Wright

Nitin Singh

Steven K Watkins

Ankit Gupta

Vandana Sapra

Christopher James Micielli

Chandan Gupta

Ashish Goel

Benjamin J Ehlers

Mark Lehmann

Mithlesh Shrivas

Syed Shakir Iqbal

Aniruddha Gupta

Regis Gubian

Lalit Mohan Singh Miyan

Venkannababu Ambati

Sakshi Gupta

Mark Shelton Cinque

Manan Kathuria

Suhas Chakravarty

Suri Roopak

Shankar Ramakrishnan

James M Giandelone

Rahul Sood

Nishant Madan

Mayank Tutwani

Shanaka Pradeep Yapa Appuhamillage Don

An integrated circuit includes an input/output (I/O) circuit configured to receive a first signal and a second signal and a fault detection circuit. The I/O circuit includes an I/O terminal, an I/O buffer, and a pull resistor having a first terminal coupled to the I/O terminal. The fault detection circuit is configured to determine whether a predetermined number of toggles of the first signal occurs while the second signal is held at a constant logic state, assert a fault indicator when the predetermined number of toggles occurs, and negate the fault indicator when the predetermined number of toggles does not occur.

Systems and methods for detecting faults in an analog input/output circuitry

An integrated circuit device includes general purpose input/output (I/O) circuitry having a transmit level shifter circuit in a transmit I/O circuit and a receive level shifter circuit in a receive I/O circuit. The integrated circuit device also includes an I/O pad which couples an output of the transmit level shifter circuit to an input of the receive level shifter circuit, a counter circuit, an inverter circuit coupled between the receive level shifter circuit and the counter circuit, and a logic gate. The logic gate includes a first input coupled to an output of the inverter circuit, a second input coupled to a counter_done signal from the counter circuit, and an output coupled to provide a data_out signal to an input of the transmit level shifter circuit.

Circuit configured to determine a test voltage suitable for very low voltage (VLV) testing in an integrated circuit

Body text indent&#x2014;does not have paragraph numbering turned on. Not needed in the Abstract. An integrated circuit device includes a digital sine wave generator configured to produce portions of a digital sine wave, a combiner circuit configured to output each of the portions of the digital sine wave combined with a respective calibration code during operation in a post-production dynamic test mode, a digital to analog converter (DAC) configured to output an analog sine wave based on the output of the combiner circuit, and a test analog to digital converter (ADC) including an input terminal directly connected to the output of the DAC, and configured to generate a second digital sine wave based on the analog sine wave.

Analog-to-digital converter (ADC) testing

A circuit including a device including a first and second node. The device operating in at least an enabled mode and a disabled mode. The circuit including a voltage control circuit. The voltage control circuit including a current source for sourcing current to or sinking current from the first node during the disabled mode and a voltage difference detector including an output for providing an indication of a measured voltage difference between the first node and the second node. The voltage control circuit includes a current source control circuit including a first input to receive the indication of the measured voltage difference and an output to control current sourced to or sinked from the first node by the current source to limit a voltage difference between the first and second node based on a comparison between the indication of the measured voltage difference and an indication of a target voltage difference.

Protection circuit

An integrated circuit includes a signal pad, an output buffer having an output coupled to the signal pad and having an enable input, an input buffer having an input coupled to the signal pad and having an enable input, a counter, and a gating circuit. The counter is enabled to start counting down a predetermined count value when a voltage on the signal pad is both higher than a predetermined low threshold voltage and lower than a predetermined high threshold voltage, wherein the predetermined low threshold voltage corresponds to a threshold below which a voltage corresponds to a logic level zero and the predetermined high threshold voltage corresponds to a threshold above which a voltage corresponds to a logic level one. The gating circuit is configured to, in response to the counter expiring, disable the input buffer and the output buffer.

Pad protection in an integrated circuit

A current leg located in a voltage domain where the current leg includes a transistor of a current mirror having a maximum voltage rating of less than the voltage of the voltage domain. The current leg includes a resistive element circuit to provide a first resistance during a normal mode of operation of the current leg and a different resistance during of a stress test of the transistor in a test mode of the circuit.

Stress test on circuit with low voltage transistor

A differential output driver circuit includes a drive path having a first output node that provides a first output differential signal and a second output node that provides a complementary second output differential signal to the first output differential signal, a current control transistor to control current of the drive path, and a current measurement resistor circuit located in the drive current path outside of a path segment between the first and second output node. Current flowing through the drive path flows through the current measurement resistor circuit, and a voltage across the current measurement resistor circuit is indicative of an amount of current flowing through the drive path. A transistor control circuit utilizes a voltage across the current measurement resistor circuit to control a control terminal of the current control transistor to control the current in the drive path based on the voltage across the current measurement resistor circuit.

Differential output driver circuit and method of operation

An integrated circuit includes a plurality of external terminal circuits, each having an external terminal. The integrated circuit includes a wakeup detector including a plurality of inputs. Each input of the plurality of inputs is coupled to an external terminal circuit. The wakeup detector generates an output signal indicative of an external terminal of the plurality of external terminal circuits being placed at a wakeup voltage. The integrated circuit includes a trigger generation circuit having a plurality of outputs in which each output is coupled to an external terminal circuit to generate a wake-up voltage at an external terminal of the external terminal circuit by coupling the external terminal to a power supply terminal of the integrated circuit to generate an indication of the external terminal being at the wakeup voltage at the wakeup detector when at least a portion of the integrated circuit is in a low power mode.

Low power mode testing in an integrated circuit

An embedded continuity test circuit is provided. An integrated circuit includes a bond pad and an oscillator circuit. The oscillator circuit is configured to generate an oscillator signal having a first frequency when the bond pad is coupled to a bond region of a package and a second frequency when the bond pad is not coupled to the bond region of the package.

Embedded continuity test circuit

A circuit includes a transmitter circuit which includes a single-to-complementary circuit, a driver stage, and a pre-emphasis control circuit. The single-to-complementary circuit generates complementary output signals from a single ended input signal. The driver stage includes inputs to receive the complementary output signals, the driver stage includes a main driver circuit and a pre-emphasis driver circuit, and the pre-emphasis driver circuit is active during transitions of the complementary output signals to provide additional current for the driver stage. The pre-emphasis control circuit includes an RC pulse generation circuit in which the RC pulse generation circuit includes a capacitance and a resistance, and the RC pulse generation circuit provides, based on edges of a signal, pulses having a duration based on an RC time constant of the capacitance and resistance. The pre-emphasis driver circuit is active to provide additional current for the driver stage in response to the pulses.

Transmitter circuit having a pre-emphasis driver circuit

An amplifier includes a differential input stage, a hysteresis stage, coupled to the differential input stage, a cascode stage coupled to the hysteresis stage, a feedback stage coupled to an output of the cascode stage and configured to provide a feedback signal to the hysteresis stage, and an output stage coupled to the output of the cascode stage. The output stage includes a hysteresis inverter coupled between the output of the cascode stage and the amplifier output.

Amplifier with hysteresis

An integrated circuit includes a transmitter having a data input coupled to receive a single-ended data signal, a reference input coupled to receive a bandgap reference, a first differential output, and a second differential output. The transmitter is configured to, during normal operation, convert the single-ended data signal at the data input into a first differential signal at the first differential output and a second differential signal at the second differential output in which the first differential signal and the second differential signal are complementary to each other. A fault detection circuit is coupled to the first and second differential outputs and is configured to detect a load short fault condition and a bandgap short condition based on the first and second differential signals at the first and second differential outputs while forcing the data input to zero.

Fault detection in a low voltage differential signaling (LVDS) system

The embodiments described herein provide analog-to-digital converters and methods that can reduce the likelihood of excessive voltage drop during the conversion of weakly driven signals while still providing the ability to perform an accurate analog-to-digital conversion. In general, the embodiments described herein reduce the likelihood of excessive voltage drop during the conversion of weakly driven signals by pre-charging the sampling capacitor used in the conversion. For example, the embodiments can apply the buffered input signal apply to the sampling capacitor for a first sampling cycle to pre-charge the sampling capacitor, and then directly apply the unbuffered input signal to the sampling capacitor for a second sampling cycle to final-charge the sampling capacitor. With the sampling capacitor charged using the two stage charging, a digital output corresponding to the charge of the sampling capacitor is generated.

Analog-to-digital conversion with sampling capacitor pre-charging

An active tamper detection circuit with bypass detection is provided. A bypass detection circuit is coupled to an active mesh loop. The bypass detector includes a voltage comparator with a variable hysteresis control circuit and a calibration engine. The bypass detector detects a change in impedance in the mesh when an attacker attempts to bypass the active loop using a wire. As part of a boot-up sequence, the calibration engine runs a hysteresis sweep on the voltage comparator and stores a hysteresis sweep boot-up signature. When bypass protection is enabled, the bypass detector runs a hysteresis sweep of the voltage comparator periodically at a predetermined interval. Each sweep generates a generated signature that is compared to the stored boot-up signature. Any signature mismatch will be signaled as an impedance mismatch, or tamper. The hysteresis step size is also programmable. The calibration engine can make small changes to the boot-up signature to allow for small voltage variations.

Active tamper detection circuit with bypass detection and method therefor

A level shifter includes a level shifting circuit, a variable bias voltage generator, and a bias voltage generator controller. The level shifting circuit is configured to level shift an input signal at a first voltage level to an output signal having a second voltage level. The second voltage level is higher than the first voltage level. The level shifting circuit includes a current mirror, an input circuit for receiving the differential input signals, and a coupling circuit for coupling the current mirror to the input circuit in response to a variable bias voltage. The variable bias voltage generator is configured to provide the variable bias voltage at one of a plurality of voltage levels. The bias voltage generator controller provides a select signal to select the voltage level from the plurality of voltage levels in response to measuring the duty cycle of the output signal to maintain the duty cycle of the output signal at a predetermined duty cycle.

Level shifter having constant duty cycle across process, voltage, and temperature variations

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Ghaziabad, India

Kumar Abhishek