Altera Corporation

Intel Corporation

Kulwinder Singh Dhanoa

Mehul Mehta

Lei Xu

Michael Fitton

Benjamin Thomas Cope

Volker Mauer

Andrew Martyn Draper

Paul Metzgen

Michael Philip Fitton

Kellie Marks

Martin Langhammer

Andrew J Bellis

Systems and methods are disclosed for enhancing network performance by using modified traffic control (e.g., rate limiting and/or scheduling) techniques to control a rate of packet (e.g., data packet) traffic to a queue scheduled by a Quality of Service (QoS) engine for reading and transmission. In particular, the QoS engine schedules packets using estimated packet sizes before an actual packet size is known by a direct memory access (DMA) engine coupled to the QoS engine. The QoS engine subsequently compensates for discrepancies between the estimated packet sizes and actual packet sizes (e.g., when the DMA engine has received an actual packet size of the scheduled packet). Using these modified traffic control techniques that leverage estimating packet sizes may reduce and/or eliminate latency introduced due to determining actual packet sizes.

Systems and methods for predictive scheduling and rate limiting

Various structures and methods are disclosed related to efficiently accessing a memory for a particular application. An embodiment of the present invention utilizes characteristics of an access pattern for a particular application to provide a more efficient organization of data in a memory. In one embodiment, the predictability in access needs for a particular application is exploited to provide a data organization method for organizing data in an SDRAM memory to support efficient access. In one embodiment, the particular application is operation under the Long Term Evolution ('LTE') standard for wireless communications. In one embodiment, associated hardware and methods are provided to, when necessary, reorder read commands and, when necessary, reorder data read from memory so that at least some of the time overhead for accessing one row can be hid behind an access of another row.

SDRAM memory organization and efficient access

Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block.

Systems and methods for interfacing between hard logic and soft logic in a hybrid integrated device

A matrix decomposition circuit is described. In one implementation, the matrix decomposition circuit includes a processing element to process a plurality of processing cells and a scheduler coupled to the processing element, where the scheduler instructs the processing element to process only required processing cells of the plurality of processing cells. In one specific implementation, the required processing cells are processing cells with non-zero inputs. Also, in one specific implementation, the matrix decomposition circuit includes an internal memory that has a rotation angles memory that stores rotation angle values calculated by the processing element, where the rotation angles memory is a first-in first-out (FIFO) memory; a systolic cell internal input values memory that stores systolic cell internal input values, where the systolic cell internal input values memory is a FIFO memory; and a systolic cell values memory that stores systolic cell values, where the systolic cell values memory is an addressable memory. In one specific implementation, where a group of Mtotal input matrices are to be decomposed to Mtotal output matrices, where Mtotal is an integer greater than one, M input matrices are fed into a decomposition circuit to decompose in parallel, where M is an integer less than or equal to Mtotal and is a minimum number required to ensure that processing element latency is hidden.

Hardware architecture and scheduling for high performance and low resource solution for QR decomposition

In a transmitter of an orthogonal frequency division multiple access (OFDMA) system, a subchannelization module generates an OFDMA symbol with data on multiple subcarriers, from received incoming data packets. An input controller applies a first formula to determine a first index of each received data packet, and stores each received data packet at an address in memory according to its first index. An output controller applies a second formula to determine the nature of the data to be carried by each subcarrier in the OFDMA symbol and, if said second formula indicates that a data subcarrier should be output, reads the data from said memory, wherein said data packets are stored in said memory at addresses such that the data can be read out at least piecewise sequentially when generating the OFDMA symbol.

Downlink subchannelization module

A ranging code present in a transmission from a transmitter to a receiver can be detected, and hence a time offset can be determined. For each of the possible ranging codes in a transmitted signal, a correlation is formed between a received signal and the ranging code for multiple subcarriers in the received signal. For multiple adjacent ranging subcarriers, the correlation is multiplied by a conjugate of the correlation of an adjacent ranging subcarrier in order to form a differential phase value. At least one ranging code in the transmitted signal can then be determined based on the differential phase values for said plurality of subcarriers. A time offset in the transmission from the transmitter to the receiver can then be determined, based on the differential phase values for the subcarriers, and based on the determined ranging code.

Ranging code detection

Circuitry for solving linear matrix equations involving a resultant matrix, an unknown matrix and a product matrix that is a product of the resultant matrix and the unknown matrix includes matrix decomposition circuitry for triangulating an input matrix to create a resultant matrix having a plurality of resultant matrix elements on a diagonal, and having a further plurality of resultant matrix elements arranged in columns below the resultant matrix elements on the diagonal. The matrix decomposition circuitry includes an inverse square root multiplication path that computes diagonal elements of the resultant matrix having an inverse square root module, and the said inverse square root module computes inverses of the diagonal elements to be used in multiplication in place of division by a diagonal element. Latency is hidden by operating on each nth row of a plurality of matrices prior to any (n+1)th row.

Solving linear matrices in an integrated circuit device

A matrix decomposition circuit is described. In one implementation, the matrix decomposition circuit includes a memory, one or more memory counters to track one or more memory counter values regarding data stored in the memory, a processing unit that calculates elements of an output matrix, and a scheduler that determines an order for calculating the elements of the output matrix, where the scheduler uses one or more memory counter values to determine whether data needed for processing an element of the output matrix is available in the memory. In one specific implementation, the scheduler schedules processing of a diagonal element of the output matrix to occur as soon as the scheduler determines that each element of the output matrix needed for calculating the diagonal element is available in the memory.

Hardware architecture and scheduling for high performance solution to cholesky decomposition

In order to reduce the crest factor of a signal for power amplification, a windowing function is applied. The windowing function that is applied is a triangular windowing function. The use of this function produces good results when those results are measured in terms of their effect on a transmitted signal in a WCDMA communications system. The filter for performing the triangular windowing function receives the signal, and applies it to a first delay element. The output from the first delay element is applied to a second delay element. An adder forms a weighted sum of the received signal and the signals at the outputs of the first delay element and the second delay element. A first accumulator is connected to receive an input from the adder and provides a first accumulator output, while a second accumulator is connected to receive an input from the first accumulator output and provides a second accumulator output.

Peak windowing for crest factor reduction

An apparatus for producing a word of a de-interleaved sequence of bits from a sequence of bits stored in a memory is described. In one embodiment, the apparatus includes a read circuit for selecting bits of the stored sequence and forming the selected bits into a word, and a logic network arranged to produce the word of the de-interleaved sequence by concatenating sections of a plurality of words produced by the read circuit. The technique can also be used to achieve interleaving, rather than de-interleaving, of a data sequence.

Data interleaving and deinterleaving involving concatenation of words read from storage

A memory controller, such as a SDRAM controller, controls the way in which data is retrieved, in order to make more efficient use of the bandwidth of the memory data bus. More specifically, when a memory access request requires multiple data bursts on the memory bus, the SDRAM controller stores the data from the multiple data bursts in respective buffers. Data is then retrieved from the buffers such that data is read from a part of the first buffer, then from the other buffers, and finally from the remaining part of the first buffer. Storing the required data in the remaining part of the first buffer avoids the need to occupy the memory bus with a new data burst.

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Windsor, United Kingdom

Kulwinder Singh Dhanoa