Intel Corporation

Qualcomm Incorporated

Tahoe Research, Ltd.

Other

Sk Hynix Nand Product Solutions Corp.

Kuljit Singh Bains

John B Halbert

James A McCall

George Vergis

Bill Nale

Christopher E Cox

Christopher P Mozak

Shigeki Tomishima

Nadav Bonen

Rajat Agarwal

Zvika Greenfield

Chong J Zhao

Robert M Ellis

Chris B Freeman

Theodore Zale Schoenborn

Michael W Williams

Suneeta Sah

Liyong Wang

Wesley Queen

Jongwon Lee

Raj K Ramanujan

Pete D Vogt

David Zimmerman

Joseph H Salmon

Joe Salmon

Alexey Kostinsky

Randy B Osborne

Peter D MacWilliams

Herbert H Hum

James E Akiyama

Michael W Leddige

Bruce Querbach

Narendra S Khandekar

Debaleena Das

Dennis W Brzezinski

Douglas L Gabel

Tomer Levy

Kjersten E Criss

John Thomas Sprietsma

Wei P Chen

James W Alexander

Howard S David

Theodros Yigzaw

Cong Li

George R Hayek

John G Holm

Sreenivas Mandava

Aniruddha Kundu

John R Goles

Narasimha R Lanka

Xiaoming Du

Klaus J Ruff

Bruce A Christenson

Chang Kian Tan

Ge Chang

Shay Fux

Saravanan Sethuraman

Shen Zhou

Akshith Vasanth

David Wyatt

David I Poisner

Murugasamy K Nachimuthu

Aaron K Martin

Brian K Langendorf

John H Crawford

Wei Wu

Mohammad Mamunur Rashid

Gary A Solomon

Jun Shi

Animesh Mishra

Nilesh V Shah

Brian S Morris

Jing Ling

Dimitrios Ziakas

Deep K Buch

Sandeep K Jain

Navneet Dour

Robert N Murdoch

Andrew M Rudoff

Subhankar Panda

David E Freker

Mariusz Oriol

Lakshmipriya Seshan

Santanu Chaudhuri

Vivek Joy Kozhikkottu

Hany M Fahmy

Narasimha Lanka

Rebecca Z Loop

Derek M Conrow

Amir Ali Radjai

Michael Gutzmann

Manish Muthal

Ronald D Anderson

Ru Yin Ng

Thomas Dean Skelton

Hussein Alameer

Hsing-Min Chen

Lohit R Yerva

Omar Avelar Suarez

Greg Lemos

A system can predict what pages of memory the system should offline based on identification of how correctable error patterns correlate to the memory architecture. The failure prediction can account for the circuit-level architecture of the memory rather than the mere number or frequency of correctable errors. A controller correlates the hardware configuration of the memory with historical error data, and generates an estimate of pages for a host operating system (OS) to offline based on predicting uncorrectable errors (UEs).

Page offlining based on fault-aware prediction of imminent memory error

A memory device can internally track row address activates for perfect row hammer tracking, incrementing an activate count for each row when an access command is received for a row. Instead of incrementing the count for each activate, the memory controller can indicate a number greater than one for the memory device to increment the count, and then indicate not to increment the count for subsequent accesses up to the number indicated. The memory controller can determine whether the row address of an activate command is one of N recent row addresses that received the access command. The memory controller can indicate an increment of zero if the row address is one of the N recent addresses, and indicate an increment of a number higher than one if the row address is not one of the N recent addresses.

Perfect row hammer tracking with multiple count increments

An apparatus is described. The apparatus includes a memory controller having a network interface and a channel interface. The channel interface is to send read, write and refresh commands into a region of a memory. The network interface is to receive memory access requests from a network, wherein the memory requests target the region of the memory. The memory requests are sent into the network by one or more host interfaces. The memory controller has bank refresh logic circuitry. The memory controller has signaling logic circuitry to send a back pressure signal to the one or more host interfaces. The back pressure signal identifies a bank of the region of the memory that is about to be refreshed by the bank refresh logic circuitry. The back pressure signal is to inform the one or more host interfaces that any memory requests that target the bank will not be serviced by the region of memory before the bank begins to be refreshed.

Per bank refresh hazard avoidance for large scale memory

A memory subsystem with error checking and scrubbing (ECS) logic on-device on the memory can adapt the rate of ECS operations in response to detection of errors in the memory when the memory device is in automatic ECS mode. The ECS logic can include an indication of rows of memory that have been offlined by the host. The ECS logic can skip the offlined rows in ECS operation counts. The ECS logic can include requests or hints by the host to have ECS operations performed. An internal address generator of the ECS logic can select between generated addresses and the hints. The system can allow a memory controller to detect multibit errors (MBEs) related to a specific address of the associated memory. When the detected MBEs indicate a pattern of errors, the memory controller triggers a row hammer response for the specific address.

Adaptive internal error scrubbing and error handling

A multi-chip device having a configurable physical interface in a logic die to on-package memory is provided. The configurable physical interface to allow a connection from a signal on the memory interface to be selected based on whether the logic die is mirrored or non-mirrored.

Logic die in a multi-chip package having a configurable physical interface to on-package memory

A memory chip includes row hammer threat detection circuitry. The memory chip includes an output. The memory chip includes backpressure signal generation circuitry coupled between the row hammer detection circuitry and the output. The backpressure signal generation circuitry is to generate a backpressure signal to be sent from the output in response to detection by the row hammer threat detection circuitry of a row hammer threat.

Method and apparatus for memory chip row hammer threat backpressure signal and host side response

A stack of memory chips and a logic chip is placed within a same package. Multiple memory chips of the stack of memory chips are divided into fractions, and multiple internal channels within the package that emanate from the logic chip are coupled to respective ones of the fractions. The logic chip has a multiplexer, including a multiplexer to multiplex a single input/output (I/O) channel of the package to the multiple internal channels.

Stacked memory chip solution with reduced package inputs/outputs (I/Os)

For a memory device where a data fetch accesses N/2 data bits, and the memory device is to transfer N bits over a data burst of length M in response to a read command, the memory device accesses the same bank twice to access the N bits. Instead of accessing N/2 bits from two different banks, the memory device accesses a single bank twice. The memory device can control the timing of the data transfer to enable sending all N data bits to the memory controller for the read command. The memory device can send data as a first transfer of burst length M/2 of a first N/2 data bit portion and a second transfer of burst length M/2 of a second N/2 data bit portion.

Double fetch for long burst length memory data transfer

Per channel thermal management techniques are described herein. In one example, a memory controller receives channel temperature information for one or more channels of one or more dies in the stack. The memory controller can then throttle commands at a channel-level based on the channel temperature information. In one example, row commands and column commands to a channel are throttled at independent rates based on the channel temperature information. In one example, a row command throttling rate or column command throttling rate is based on a ratio of alternating on-time to off time of throttling signals, or a window of time in which commands are enabled or disabled to a channel. In one example, the row and column command throttling signals can be staggered across channels or pseudo channels.

Per channel thermal management techniques for stacked memory

A system can predict memory device failure through identification of correctable error patterns based on the memory architecture. The failure prediction can thus account for the circuit-level of the memory rather than the mere number or frequency of correctable errors. A failure prediction engine correlates hardware configuration of the memory device with correctable errors (CEs) detected in data of the memory device to predict an uncorrectable error (UE) based on the correlation.

Uncorrectable memory error prediction

A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS)

A memory is described. The memory includes row buffer circuitry to store a page. The page is divided into sections, wherein, at least one of the sections of the page is to be sequestered for the storage of meta data, and wherein, a first subset of column address bits is to: 1) define a particular section of the page, other than the at least one sequestered sections of the page, whose data is targeted by a burst access; and, 2) define a field within the at least one of the sequestered sections of the page that stores meta data for the particular section.

Dynamic random access memory (DRAM) with scalable meta data

A memory device having on-die error checking and correction (ECC) circuitry can provide uncorrected data in response to a read command. The ECC circuitry can perform error correction for errors detected, generating the corrected data in parallel with providing the uncorrected data. The memory device stores the corrected data internally to the memory device. When an error is detected, the memory device provides an indication to the memory controller, which can then request the corrected data.

Reduction of latency impact of on-die error checking and correction (ECC)

A memory chip is described. The memory chip includes storage cells along a row of the memory chip's storage cell array to store a count value of the row's activations and error correction code (ECC) information to protect the count value. The memory chip includes ECC read logic circuitry to correct an error in the count value. The memory chip includes a comparator to compare the count value against a threshold. The memory chip includes circuitry to increment the count value if the count value is deemed not to have reached the threshold and ECC write logic circuitry to determine new ECC information for the incremented count value, and write driver circuitry to write the incremented count value and the new ECC information into the storage cells. The memory chip includes circuitry to cause the row to be refreshed if the count value is deemed to have reached the threshold.

Memory chip with per row activation count having error correction code protection

Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

Techniques to couple high bandwidth memory device on silicon substrate and package substrate

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Olympia, WA, United States of America

Kuljit Singh Bains