General Datacomm, Inc.

Kuldip S Bains

Javier R Rojas

Chung C Liang

The invention routes SVC ATM call setups by utilizing one of a plurality of designated transit lists (DTLs) stored at an originating node. The DTLs describe all routes in the network from the originating node to endpoint destinations. When a call setup message is received at the originating node, it inserts a desired DTL as an information element (IE) of the setup message. Each DTL is formatted as a concatenation of elements with each element including the node ID and output ports of each successive node in the route. Preferably, each element of the DTL includes flags such as a 'process' flag which indicates whether an element of the DTL has been processed by a node, a 'link up' flag which indicates that an alternative route is available between two nodes should the preferred route be down, a 'bandwidth' flag which allows the alternate link to be used if the preferred link is busy, and a 'last node' flag which is used in the last element of the concatenated DTL. If the 'last node' flag is not set, the destination node internally generates a route ID as the last element based on the destination address specified in an IE for the call. As the DTL IE is passed from node to node along the connection path, the receiving node inserts the input port at which it received the call setup message as well as a VPI/VCI into its element of the DTL. At its destination, the DTL is attached to a CONNECT request message which is returned to the source node.

Systems and methods for routing ATM switched virtual circuit calls

Methods for quickly determining loss of synchronization and for quickly reestablishing synchronization of a sub-aggregate frame having primary and secondary frames and contained within an independently synchronized aggregate are provided. In determining loss of synchronization, synch bits are located in the secondary frame such that when the composite subaggregate frame is synchronized the synch bits are chosen to be inserted into the same predetermined position in the aggregate. The synch bits are provided with values such that a collection of synch bits of a composite frame provides an internally non-repeating pattern. By comparing bit values received in the predetermined location of the aggregate at the synch bit rate with the non-repeating pattern, a determination is made as to whether synchronization has been lost. To reestablish synchronization, during data receipt, the bits located in the predetermined synch bit location in the aggregate frame are sequentially inserted into a number of buffers, the number being equal to the frame rate of the subaggregate divided by the synch rate of the synch bits. Then, upon loss of synchronization, a local pointer value is stored upon receipt of a synch bit candidate, the bit patterns in the buffers are scanned to find the buffer containing the internally non-repeating synch pattern, and a pointer correction indication is determined by comparing the local pointer value to a system pointer value dictated by the buffer found to contain the synch bits, and the phase of the internally non-repeating synch pattern in that buffer.

Multiplexer frame synchronization technique

An algorithm for ordering selects for a plurality of channels to be multiplexed into a frame is provided. A channel ready counter and a channel select position counter for each of the channels to be multiplexed are initialized. The first and succeeding channel selects are chosen based primarily on the respective values of the channel ready counters such that a channel having a ready counter of relative higher value is always selected before a channel having a ready counter of relative lower value. Where channel ready counter integer values of more than one channel are equal, the select is chosen on the secondary basis of channel rate, with the highest rate channel of the highest ready count contributing first. After a select is made, the ready counter of the selected channel is determined, and the position counters of the channels are decremented by a value corresponding to the number of selects for that channel in the frame. If the position counter of a channel reach zero or goes negative as a result of the decrementing, the position counter of that channel is increased by the total number of selects in the frame, and the ready counter for that channel is incremented by one. After such updating, another selection for the frame may be made based on the ready counter values of the channels. The provided algorithm guarantees that no channel will ever have an excursion of more than one bit available for placement in the frame.

Algorithm for selecting channels for multiplexer frame

Methods are provided for multiplexing a plurality of channels on to a sub-aggregate of an aggregate line so as to substantially minimize total frame length. In a preferred method, channel data rates are expressed as a sum of a plurality of predetermined subchannel data rates, and the number of times each predetermined subchannel data rate is used to express a channel data rate of a channel to be multiplexed is accumulated. Given a predetermined primary frame rate (P) such as 8Khz for a DACs compatible multiplexer, and a tertiary frame rate (T) chosen as the greatest common denominator of the subchannel data rates, an optimal secondary frame rate (S) may be found by minimizing for a plurality of different secondary frame rates the sum of (P/S) F1 plus (S/T)F2, where F1 represents the number of calls of the primary frame to the secondary frame, and F2 represents the number of calls of the secondary frame to the tertiary frame. Where different primary frame rates may be used, the sum of (A/P) plus (P/S)F1 plus (S/T)F2 is minimized to find primary and secondary frame rates which will permit an optimally small total frame length, given the sub-aggregate rate A.

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Watertown, CT, United States of America

Kuldip S Bains