Qualcomm Incorporated

Kuldeep Singh Chahal

Darshan Kumar Nandanwar

Siddesh Halavarthi Math Revana

Srinivasa Kumar Munivenkata Gowda

Nilesh Dhavlikar

Small timing margins between the period of a clock and the propagation delays of critical signal paths in an IC at a given supply voltage create a risk for errors in response to voltage droop. Increasing the supply voltage increases the timing margin but also increases power consumption. A margin management circuit includes a delay path having a configurable delay that corresponds to the propagation delay of a critical signal path. Based on a detected timing margin of the delay path, a frequency adjustment signal is generated to adjust the clock frequency to adjust the timing margin. In response to a reduction in the timing margin, due to a sudden voltage droop, the clock frequency may be adjusted to avoid errors. In some examples, the frequency of the clock is compared to a desired frequency and the supply voltage is adjusted to restore the desired frequency.

Power saving circuits to adjust frequency according to dynamic timing margin changes and adjust supply voltage to restore desired frequency and related methods

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Noida, India

Kuldeep Singh Chahal