Globalfoundries Inc.

International Business Machines Corporation

Kuldeep Amarnath

Judson Robert Holt

Brian Joseph Greene

Michael John Hargrove

William K Henson

Rohit Pal

Michael D Steigerwalt

Johan W Weijtmans

Andy T Nguyen

Ravi Prakash Gutala

Srikanth Balaji Samavedam

Kevin J Yang

Jia Feng

Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening.

Methods of forming replacement gate structures with a recessed channel

Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including a first region of a first doping type, a second region of the first doping type spaced from the first region, a drift region of the first doping type positioned between the first region and the second region, and regions of the opposite doping type. A mask covering both the drift region and the regions of the opposite doping type is formed. Then, a source/drain ion implantation is performed into the first region and the second region. The mask prevents the drift region and the regions of the opposite doping type from receiving the source/drain ion implantation.

Methods for fabricating integrated circuits with drift regions and replacement gates

Methods and structures for a double-sided semiconductor structure using through-silicon vias (TSVs) are disclosed. The double-sided structure has functional circuits on both the front and back sides, interconnected by one or more TSVs. In some embodiments, multiple double-sided structures are combined to create 3D semiconductor structures with increased circuit density.

Double-sided semiconductor structure using through-silicon vias

A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

Self-aligned embedded SiGe structure and method of manufacturing the same

One illustrative method disclosed herein includes forming first and second FinFET devices in and above a first region and a second region of a semiconducting substrate, respectively, performing a first ion implantation process through a patterned mask layer to implant nitrogen into the second region, removing the patterned mask layer, performing a second ion implantation process to implant oxygen atoms into both the first and second regions, performing a heating process to form a layer of insulating material at least in the first region and performing at least one etching process to define at least one first fin in the first region and to define at least one second fin in the second region, the second fin being taller than the first fin.

Methods of forming FinFET semiconductor devices with different fin heights

Growing community of inventors

San Jose, CA, United States of America

Kuldeep Amarnath