Micron Technology Incorporated

Sandisk Technologies Inc.

Kulachet Tanpairoj

Jianmin Huang

Harish Reddy Singidi

Ting Luo

Kishore Kumar Muchherla

Ashutosh Malshe

Sebastien Andre Jean

Preston Allen Thomson

Peter Sean Feeley

Xiangang Luo

Sampath K Ratnam

Jonathan Scott Parry

Qing Liang

Stephen D Hanna

David Aaron Palmer

Scott Anthony Stoller

Christian M Gyllenskog

Nadav Grosz

Sean L Manion

Carla L Christensen

Deping He

Devin M Batutis

Nian Niles Yang

Christopher Joseph Bueb

Tomoko Ogura Iwasaki

Chun Sum Yeung

Tyson M Stichka

John Zhang

Steven Theodore Sprouse

Chris Avila

Gautam Ashok Dusija

Chris Nga Yee Avila

Lawrence Celso Miranda

Sheyang Ning

Lee M Gavens

Yichao Huang

Xiaolai Zhu

Hong Lu

Bhuvan Khurana

Ken Jianhui Hu

A method includes identifying, by a processing device, a common pool of blocks comprising a first plurality of blocks allocated to system data and a second plurality of blocks allocated to user data; determining whether user data has been written to the second plurality of blocks within a threshold period of time; and responsive to determining that the user data has not been written to the second plurality of blocks within the threshold period of time, allocating a block from the second plurality of blocks to the first plurality of blocks.

Using a common pool of blocks for user data and a system data structure

A method includes writing, to a first data structure, indices corresponding to address locations of a logical-to-physical (L2P) data structure that maps a plurality of logical block addresses (LBAs) associated with the L2P data structure, initiating performance of a media management operation involving one or more memory blocks in which data associated with the LBAs is written, and refraining from rewriting particular entries in the L2P table that correspond to LBAs whose index in the first data structure is a particular value during performance of the media management operation.

Virtual indexing in a memory device

Methods, systems, and devices for data migration techniques are described. The memory system may receive a command associated with a write operation from a host device. The memory system may determine whether to use a data migration technique for writing data to the memory device based on receiving the command. In some cases, the memory system may select a tri-level write format instead of a quad-level write format for writing the data and write the data using the tri-level write format. The memory system may convert the data from the tri-level write format to the quad-level write format based on writing the data using the tri-level write format.

Data migration techniques

Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

Sequential data optimized sub-regions in storage devices

An apparatus can include a block program erase count (PEC) component. The block PEC component can monitor a quantity of program erase counts (PECs) for each particular type of block of a non-volatile memory array. The block PEC component can further determine which block of the superblock to write host data to next based on the quantity of PECs. The block PEC component can further write host data to the determined block.

Memory sub-system for monitoring mixed mode blocks

An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a reset signal from a host computer system in communication with the memory system; identify, by decoding the reset signal, a host event specified by the reset signal; and process the identified host event.

Notifying memory system of host events via modulated reset signals

An example apparatus includes a media management superblock component configured to determine that a quantity of blocks of a superblock of a non-volatile memory array are bad blocks; compare the quantity of bad blocks to a bad block criteria; and write host data to the superblock with the quantity of bad blocks in response to the quantity of bad blocks meeting the bad block criteria. The use of the superblock with a particular quantity of bad block minimizes yield loss for non-use of partial superblocks.

Memory sub-system using partial superblocks

Various examples are directed to devices and methods involving a host device and a memory system, the memory system comprising a memory controller and a plurality of memory locations. The memory system may send to the host device a first message describing background operations to be performed at the memory system. The memory system may receive from the host device a second message indicating permission to execute the background operations and may begin to execute at least one background operation.

Performance of memory system background operations

Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules that are evaluated using the state of the NAND device. In some examples, the SLC cache migration process may utilize a number of NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data.

UFS based idle time garbage collection management

Described are systems and methods for performing memory programming operations in the overwrite mode. An example memory device includes: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: responsive to identifying a first data item to be stored by a portion of the memory array, causing a first memory programming operation to be performed to program, to a first target threshold voltage, a set of memory cells included by the portion of the memory array; and responsive to identifying a second data item to be stored by the portion of the memory array, causing a second memory programming operation to be performed to program the set of memory cells to a second target threshold voltage exceeding the first target threshold voltage.

Overwrite mode in memory programming operations

Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

Secure erase for data corruption

Methods, systems, and devices for status information retrieval for a memory device are described. In some examples, a memory device may include a set of status registers, each of which may be configured to store a corresponding set of status information. For example, at least some of the status registers may store status information for a corresponding portion of the memory device. The memory device may receive a command to output status information along with an indication of one or more particular status registers from which to output status information in response to the command. In response to the command and indication, the memory device may output status information from any quantity of status registers, including any type of status information, in a single stream or burst.

Status information retrieval for a memory device

Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

Uncorrectable ECC

Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

Read voltage calibration based on host IO operations

Growing community of inventors

Santa Clara, CA, United States of America

Kulachet Tanpairoj