National Taiwan University

Taiwan Semiconductor Manufacturing Comp. Ltd.

Asml Netherlands B.v.

Kuen-Yu Tsai

Miin-Jang Chen

Chee-Wee Liu

Samuel C Pan

Chun-Hung Liu

Meng-Fu You

Yi-Chang Lu

Si-Chen Lee

Bo-Sen Chang

Alek Chi-Heng Chen

Shiau-Yi Ma

Wei-Jhih Hsieh

Jia-Han Li

Chooi-Wan Ng

Hoi-Tou Ng

Yi-Sheng Su

Philip C W Ng

Pei-Lin Tien

Sheng-Yung Chen

A method for forming a semiconductor device is provided. A first patterned mask is formed on the substrate, the first patterned mask having a first opening therein. A second patterned mask is formed on the substrate in the first opening, the first patterned mask and the second patterned mask forming a combined patterned mask. The combined patterned mask is formed having one or more second openings, wherein one or more unmasked portions of the substrate are exposed. Trenches that correspond to the one or more unmasked portions of the substrate are formed in the substrate in the one or more second openings.

Method for non-resist nanolithography

Methods for non-resist nanolithography

A process for fabricating an integrated circuit is provided. The process includes providing a substrate, forming a hard mask upon the substrate by one of atomic-layer deposition and molecular-layer deposition, and exposing the hard mask to a charged particle from one or more charged particle beams to pattern a gap in the hard mask. In the alternative, the process includes exposing the hard mask to a charged particle from one or more charged-particle beams to pattern a structure on the hard mask.

Charged-particle-beam patterning without resist

The present disclosure relates to a curve-fitting procedure for determining proximity effect device parameters in semiconductor fabrication. Methods presented herein are adapted to determine the impact of narrow width related effects on device characteristics by comparing two-dimensional (2D) and/or three-dimensional (3D) device simulations. Methods presented herein are adapted to determine the accuracy of conventional extraction methods utilizing non-rectangular gate device simulation.

Determining proximity effect parameters for non rectangular semiconductor structures

A process for fabricating an integrated circuit is provided. The process includes providing a substrate and forming a hard mask on the substrate. The hard mask may be formed by atomic-layer deposition (ALD) or molecular-layer deposition (MLD). The process also includes disposing an exposure mask over the hard mask and exposing the exposure mask to a patterning particle to pattern a gap in the hard mask. The patterning particle may be, for example, a photon or a charged particle.

Projection patterning with exposure mask

Calibration of models for manufacturing processes that are subject to circuit layout proximity effects is performed, including optical proximity correction (OPC) model calibration. A target structure is produced using a layout and a manufacturing process. The target structure is illuminated and an electromagnetic scattering property is detected. A manufacturing process model for simulation of the manufacturing process is produced, which comprises at least one manufacturing process parameter determining a model electromagnetic scattering property using the manufacturing process model and the layout. The model electromagnetic scattering property is compared to the detected electromagnetic scattering property and based on the result of the comparison, calibrated manufacturing process parameters are output for calibrating the manufacturing process model. The determining and the layout may include determining structural information corresponding to the target structure using the manufacturing process model and determining the model electromagnetic scattering property using the structural information.

Method for calibrating a manufacturing process model

A method for establishing a parametric model of a semiconductor process is provided. A first intermediate result is generated according to layout data and a non-parametric model of the semiconductor process. A first response is obtained according to the first intermediate result. A specific mathematical function is selected from a plurality of mathematical functions, and the parametric model is obtained according to the specific mathematical function. A second intermediate result is generated according to the layout data and the parametric model. A second response is obtained according to the second intermediate result. It is determined whether the parametric model is an optimal model according to the first and second responses.

Method and system for establishing parametric model

The present disclosure relates to a curve-fitting procedure for determining proximity effect device parameters in semiconductor fabrication. Methods presented herein are adapted to determine the impact of narrow width related edge effects on device characteristics by comparing two-dimensional (2D) and/or three-dimensional (3D) device simulations. Methods presented herein are adapted to determine the accuracy of conventional extraction methods utilizing non-rectangular gate device simulation.

Determining proximity effect parameters for non-rectangular semiconductor structures

A method for compensating an effect of a patterning process is illustrated. The main concept of the method for compensating the effect of the patterning process is to add or subtract the correction amounts for all segments according to the set of the comparison values at the set of the evaluation points. Compared with the delta-chrome optical proximity correction method, the run time of the method for compensating the effect of the patterning process is reduced, the memory usage of the method for compensating the effect of the patterning process not increased, and the correction accuracy of the method for compensating the effect of the patterning process is not reduced.

Method for compensating effect of patterning process and apparatus thereof

A method for compensating proximity effects of particle beam lithography processes is provided. The method includes the following steps. A control pattern is provided. A dissection process is provided. A set of control points are provided. The control pattern is defined as an input pattern of a lithography process. A target pattern is provided. A set of target points are produced. A set of target measurement values are provided. An actual pattern is defined. A set of actual measurement values are provided. A set of comparison values are calculated. An adjusting strategy is provided. A corrected pattern is produced. The corrected pattern is defined as an updated input of the lithography process.

Method for compensating proximity effects of particle beam lithography processes

A method which directly incorporates patterning fidelity into the design of a patterning system is provided. A production result of a target pattern is simulated according to a set of design parameters to obtain a simulated pattern. The target pattern is compared with the simulated pattern to obtain a patterning fidelity, and the values of the set of design parameters of the patterning system are adjusted according to a target patterning fidelity to optimize the values of the set of design parameters of the patterning system.

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Taipei, Taiwan

Kuen-Yu Tsai