International Business Machines Corporation

Globalfoundries Inc.

University of Michigan

Princeton University

Forrest, Stephen R.

Lee, Kyusang

Shiu, Kuen-Ting

Zimmerman, Jeramy

Kuen-Ting Shiu

Cheng-Wei Cheng

Devendra K Sadana

Ning Li

Yanning Sun

Shu-Jen Han

Jeehwan Kim

Amlan Majumdar

Edward William Kiewra

Can Bayram

Effendi Leobandung

Tak H Ning

Ko-Tao Lee

Stephen W Bedell

Dechao Guo

Jeng-Bang Yau

Masaharu Kobayashi

Uzma B Rana

Stephen R Forrest

Anirban Basu

Norma Edith Sosa Cortes

Keith E Fogel

Isaac Lauer

Jack Oon Chu

Katherine Lynn Saenger

Jae-Woong Nah

Augustin J Hong

Szu-Lin Cheng

Ghavam G Shahidi

Martin Michael Frank

Wilfried Haensch

Tze-Chiang Chen

Christos Dimitrios Dimitrakopoulos

Frank Robert Libsch

David Lee Rath

Brent A Wacaser

Leathen Shi

Sanghoon Lee

Jeramy David Zimmerman

Kyusang Lee

Jin-Hong Park

Shu-Jen Hen

Shashank S Agashe

Szu Lin Cheng

Guy M Cohen

Christian Lavoie

Paul Michael Solomon

Zhen Zhang

John Albrecht Ott

Tayfun Gokmen

Alessandro Cesare Callegari

Guodan Wei

Ryan M Martin

A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.

Direct growth of lateral III-V bipolar transistor on silicon substrate

A semiconductor device including a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure. The semiconductor device further includes a III-V optoelectronic device that is present in direct contact with the isolation dielectric material in a first region of the second portion of the substrate structure. A dielectric wave guide is present in direct contact with the isolation dielectric material in a second region of the second portion of the substrate structure.

III-V photonic integrated circuits on silicon substrate

A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch.

Wafer bonded solar cells and fabrication methods

A structure includes an optoelectronic device having a Group IV substrate (e.g., Si); a buffer layer (e.g. SiGe) disposed on the substrate and a first distributed Bragg reflector (DBR) disposed on the buffer layer. The first DBR contains alternating layers of doped Group IV materials (e.g., alternating layers of SiGe, where 0.8&#x3c;y&#x3c;1, and SiGe, where 0.2&#x3c;z&#x3c;0.4) that are substantially transparent to a wavelength of interest. The structure further includes a strained layer of a Group III-V material over the first DBR and a second DBR over the strained layer. The second DBR contains alternating layers of electrically conductive oxides (e.g., ITO/AZO) that are substantially transparent to the wavelength of interest. Embodiments of VCSELs and photodetectors can be derived from the structure. The strained layer of Group III-V material can be, for example, a thin layer of InGaAs having a thickness in a range of about 2 nm to about 5 nm.

Resonant cavity strained group III-V photodetector and LED on silicon substrate and method to fabricate same

A method comprises providing a sacrificial release layer on a base substrate; forming a device layer on the sacrificial release layer; depositing a metal stressor layer on the device layer; etching the sacrificial release layer; and using epitaxial lift off to release the device layer and the metal stressor layer from the base substrate.

Stress assisted wet and dry epitaxial lift off

A method of forming a semiconductor device is provided. The method includes depositing an aluminum-base interlayer on a silicon substrate, the aluminum-base interlayer having a thickness of less than about 100 nanometers; and growing a III-V compound material on the aluminum-base interlayer. The aluminum-base interlayer deposited directly on silicon allows for continuous and planar growth of III-V compound materials on the interlayer, which facilitates the manufacture of high quality electronic devices.

Integration of III-V compound materials on silicon

Resonant cavity strained Group III-V photodetector and LED on silicon substrate and method to fabricate same

A heteroepitaxially grown structure includes a substrate and a mask including a high aspect ratio trench formed on the substrate. A cavity is formed in the substrate having a shape with one or more surfaces and including a resistive neck region at an opening to the trench. A heteroepitaxially grown material is formed on the substrate and includes a first region in or near the cavity and a second region outside the first region wherein the second region contains fewer defects than the first region.

Enhanced defect reduction for heteroepitaxy by seed shape engineering

An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second III-V semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.

III-V field effect transistor on a dielectric layer

A method of forming a semiconducting material includes depositing a graded buffer on a substrate to form a graded layer of an indium (In) containing III-V material, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 atomic % (at. %) based on total atomic weight of InGa or InAl; and forming a layer of InGaAs on the graded layer, the layer of InGaAs comprising about 25 to about 100 at. % In based on total atomic weight of InGa.

Preparation of low defect density of III-V on Si for device fabrication

Growing community of inventors

White Plains, NY, United States of America

Kuen-Ting Shiu