Macronix International Co., Ltd.

Kuen Long Chang

Ken Hui Chen

Chun Hsiung Hung

Chia-Feng Cheng

Yu Chen Wang

Su Chueh Lo

Su-Chueh Lo

Yi-Fan Chang

Chin Hung Chang

Wen Chiao Ho

Nai Ping Kuo

Chun-Hsiung Hung

Ken-Hui Chen

Chin-Hung Chang

Cheng Ming Yih

Kuo Yu Liao

Jian Shing Liu

Ta Kang Chu

Chu Ching Wu

Cheng-Ming Yi

A memory device includes an error code generator, one or more first pins coupled to an external data bus, and one or more second pins coupled to an external system interface. The one or more first pins output data chunks to the data bus during a period of memory operation; and the error code generator is configured to transmit a status code via the one or more second pins during the period of memory operation. The status code indicates at least one of an error was detected, an error was detected and corrected, or an error was detected and not corrected.

Method and device for monitoring data error status in a memory

An electronic device includes a processor coupled to a memory device, through a data bus to receive and transmit bits on the data bus. The processor is configured to transmit a message including a first bit indicative of controlling the data bus, address bits indicative of an address identifying the memory device, and a second bit indicative of whether the processor intends to read data from or write data to the memory device; and transmit a third bit indicative of a mode of operation of the memory device.

Electronic device and data exchange method including protocol indicative of modes of operation

A method for monitoring data error status of a memory device includes generating, by a memory controller, a data status indication code indicating error status of a data chunk transmitted by the memory controller and outputting, by the memory controller, the data status indication code to a user interface.

In accordance with the disclosure, there is provided a memory device configured to implement an error detection protocol. The memory device includes a memory array and a first input for receiving a control signal corresponding to a command cycle. The memory device also includes a second input for receiving an access control signal during a command cycle and for receiving an error detection signal during the command cycle, wherein the error detection signal includes information corresponding to the access control signal. The memory device further includes control logic configured to verify the correctness of the access control signal by a comparison with the error detection signal and perform an operation on the memory array during the command cycle when the correctness of the access control signal is verified.

Device and method for detecting controller signal errors in flash memory

A memory device includes a variable strobe interface configured to select one of a data queue strobe signal or a system clock signal to signal initiation of data receipt at the memory device.

Memory device with variable strobe interface

A method for outputting data error status of a memory device includes generating data status indication codes indicating error status of data chunks transmitted by a memory controller, and combining the data status indication codes with corresponding data chunks to generate an output signal, and outputting the output signal to a data bus pin.

Monitoring data error status in a memory

A method for command processing in a memory controller includes receiving a serial input signal including a series of binary digits, capturing the binary digits at ones of odd locations or even locations of the serial input signal to form a first sub-series, capturing the binary digits at other ones of the odd locations or the even locations of the serial input signal to form a second sub-series, comparing the first and second sub-series, and performing a command represented by the first sub-series, if the first and second sub-series are complementary to each other.

Method and device for processing serial binary input by comparing binary digits at even and odd locations of the input

Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines.

Method and apparatus of performing an erase operation on a memory integrated circuit

Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.

A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully.

Method and apparatus for protection of non-volatile memory in presence of out-of-specification operating voltage

The present invention provides a novel method in altering the sequence of multi-level-cell programming in a multi-bit-cell of a nitride trapping memory cell that reduces or eliminates voltage threshold shifts between program steps while avoiding the suppression in the duration of a read window caused by a complementary bit disturbance. In a first embodiment, the present invention programs the multi-level cell in a multi-bit-cell having four bits in the following order: programming a third program level (level), programming a first program level (level) and a second program level (level) to level, and programming the second program level from the first program level. In a second embodiment, the present invention programs the multi-level cell in the multi-bit-cell having four bits in the following order: programming a third program level (level), programming a second program level (level), and programming a first program level (level).

Multi-level-cell programming methods of non-volatile memories

The present invention provides a novel method in altering the sequence of multi-level-cell programming in a multi-bit-cell of a nitride trapping memory cell that reduces or eliminates voltage threshold shifts between program steps while avoiding the suppression in the duration of a read window caused by a complementary bit disturbance. In a first embodiment, the present invention programs the multi-level cell in a multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a first program level (level1) and a second program level (level2) to level 1, and programming the second program level from the first program level. In a second embodiment, the present invention programs the multi-level cell in the multi-bit-cell having four bits in the following order: programming a third program level (level3), programming a second program level (level2), and programming a first program level (level 1).

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Taipei, Taiwan

Kuen Long Chang