Macronix International Co., Ltd.

National Science Council of R.o.c.

Macronix Internationalco., Ltd.

Kuen-Long Chang

Chun-Hsiung Hung

Ken-Hui Chen

Chin-Hung Chang

Su-Chueh Lo

Nai-Ping Kuo

Wen-Chiao Ho

Chun-Yi Lee

Yu-Chen Wang

Chia-He Liu

Chia-Jung Chen

Shih-Chang Huang

Chun Hsiung Hung

Ming-Chih Hsieh

Chia-Feng Cheng

Ray-Lin Wan

Chang-Ting Chen

I-Long Lee

Chuan-Ying Yu

Yu-Meng Chaung

Yung-Feng Lin

Shang-Chi Yang

Yi-Fan Chang

Wu-Chin Peng

Yin-Shang Liu

Weitong Chuang

Bo-Chang Wu

Chao-Hsin Lin

Han-Sung Chen

Tom D Yiu

Tzeng-Huei Shiau

Chun-Yu Liao

Chih-Ting Hu

Yu-Lan Kuo

Wen Chiao Ho

Chin Hung Chang

Cheng Ming Yih

Jeng-Kuan Lin

Tien-Shin Ho

Hsieh-Ming Chih

Kuan-Ming Lu

Yi-Chun Shih

Fuchia Shone

Ken Hui Chen

Shin-Jang Shen

Ray L Wan

Yung Feng Lin

Chien-Hsin Liu

Chia-Shing Chen

Yao-Wu Cheng

Ching-Chung Lin

Yuan-Chang Liu

Kuo Yu Liao

Yufe Feng Lin

Jieh-Tsorng Wu

Yufe-Feng Lin

Jian Shing Liu

Ta Kang Chu

Chu Ching Wu

Chen-Chia Fan

Hun-Song Chen

Min-Hsiung Meng

Yulan Kuo

Chuan Ying Yu

Hsieh Ming Chih

Su-Chuch Lo

Chao Hsin Lin

Cheng-Chi Liu

Tzu-Ting Chiu

Tzeng-Hei Shiau

A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.

PUF applications in memories

A memory apparatus and a control method are provided. The memory apparatus includes a non-volatile memory array having plural memory groups, and the control method is applied to the non-volatile memory array. The memory groups jointly share a first well, and the control method is applied to the non-volatile memory array. A first memory group among the memory groups is erased according to a first erase command after the memory apparatus is power-on, and a first amount of the memory groups are recovered in a first erase-recover procedure after the first memory group is erased. A second memory group among the memory groups is erased according to a second erase command after the first erase-recover procedure, and a second amount of the memory groups are recovered in a second erase-recover procedure after the second memory group is erased. The first amount is greater than the second amount.

Memory apparatus and associated control method for reducing erase disturb of non-volatile memory

A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port, the multi-address read operation including receiving a first address and a second address using the at least one signal line before outputting data.

Method and system for enhanced multi-address read operations in low pin count interfaces

A memory chip comprises a first memory controller, a first data storage zone, a security unit and an address configuration unit. The first data storage zone is coupled to the first memory controller, and represented by a first physical address range. The security unit is coupled to the first memory controller. The address configuration unit is coupled to the first memory controller. The memory chip is configured to be coupled between a host controller and another memory chip. The another memory chip comprises a second data storage zone represented by a second physical address range. The address configuration unit records one or more relationships of a logical address range corresponding to the first physical address range and the second physical address range. The security unit is configured to encrypt and decrypt data in the first data storage zone and the second data storage zone.

Memory chip having security verification function and memory device

An integrated circuit includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently.

Method and system for a serial peripheral interface

A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port in the input mode, the multi-address read operation including receiving a first address and a second address using the at least one signal line in the input mode before switching to the output mode, switching to the output mode and outputting data identified by the first address using the at least one signal line.

Method and system for enhanced read performance in low pin count interface

A system and method use a physical unclonable function in a PUF circuit on an integrated circuit to generate a security key, and stabilize the security key by storage in a set of nonvolatile memory cells. The stabilized security key is moved from the set of nonvolatile memory cells to a cache memory, and utilized as stored in the cache memory in a security protocol. Also, data transfer from the PUF circuit to the set of nonvolatile memory cells can be disabled after using the PUF circuit to produce the security key, at a safe time, such as after the security key has been moved from the set of nonvolatile memory cells to the cache memory.

Stable physically unclonable function

A memory device can include a memory, and an interface to receive a memory command sequence. A message authentication code MAC is provided with the command sequence. Control circuits on the device include a command decoder to decode a received command sequence and to execute an identified memory operation. A message authentication engine includes logic to compute a value of a message authentication code to be matched with the received message authentication code based on the received command sequence and a stored key. The device can store a plurality of keys associated with one or more memory zones in the memory. Logic on the device prevents completion of the memory operation identified by the command sequence if the value computed does not match the received message authentication code.

Security memory scheme

An integrated circuit device can comprise addressable memory, and a receiver. Data integrity logic can be coupled to the input data path and configured to receive a data stream having a reference address, and a plurality of data chunks with data integrity codes. Also, the data integrity logic can include a configuration store to store configuration data for the data integrity checking. Also, the integrated circuit can include logic to parse the data chunks and the data integrity codes from the data stream, and logic to compute computed data integrity codes of data chunks in the received data stream, and compare the computed data integrity codes with received data integrity codes to test for data errors in the received data stream. The data integrity logic includes logic responsive to the configuration data that control the data integrity logic. In one aspect, the data integrity data indicates a floating boundary data integrity mode or a fixed boundary data integrity mode.

Configurable data integrity mode, and memory device including same

A memory system has a plurality of memory devices coupled with a hub in discrete and shared port arrangements. A plurality of bus lines connect the plurality of memory devices to the hub, including a first subset of bus lines connected in a point-to-point configuration between the hub and a particular memory device, and a second subset of bus lines connected to all the memory devices in the plurality of memory devices including the particular memory device. Bus operation logic is configured to use the first subset of bus lines in a first operation accessing the particular memory device while simultaneously using the second subset of bus lines in a second operation accessing a different selected memory device of the plurality of memory devices.

I/O bus shared memory system

A device which can be implemented on a single packaged integrated circuit or a multichip includes a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce an initial key and to store the initial key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The device can include logic to use a random number generator to generate a random number, and logic to combine the initial key and the random number to produce an enhanced key. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce the initial key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.

Non-volatile memory with physical unclonable function and random number generator

A memory device comprises a memory array with I/O path and security circuitry coupled to the I/O path of the memory array. The memory device comprises control circuitry, responsive to configuration data, to invoke the security circuitry. The memory device comprises a configuration store, storing the configuration data accessible by the control circuitry to specify location and size of a security memory region in the memory array. Responsive to an external command and the configuration data, the control circuitry can be configured to invoke the security circuitry on an operation specified in the external command in response to accesses into the security memory region, or to not invoke the security circuitry in response to accesses to outside the security memory region.

Configurable security memory region

A data receiving stage circuit of a memory circuit receives a serial input signal and a chip enable signal. A data writing circuit of the memory circuit generates at least one of a command signal and a data signal according to the serial input signal. A power supply circuit of the memory circuit generates an operating voltage for a memory cell array to perform a data access operation. A data output stage circuit of the memory circuit outputs a readout data. A controller of the memory circuit performs a switching operation of an operating state of the memory circuit according to a change of the chip enable signal. The controller determines a disable or enable state of the data receiving stage circuit, the data writing circuit, the power supply circuit, and the data output stage circuit according to the operating state.

Memory circuit

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Taipei, Taiwan

Kuen-Long Chang