Texas Instruments Corporation

Kueing L Chen

Roland H Pang

A method and structure for protecting an integrated circuit from electrostatic discharges are disclosed. A Shockley diode (22) is connected to an input bond pad (12) and to a MOSFET transistor (17) which is desired to be protected. The normally high breakdown voltage required to drive the Shockley diode (22) into conduction is reduced by providing a trigger transistor (24) for prematurely triggering the diode (22). When the base-collector junction of the common emitter configured trigger transistor (24) is driven into avalanche breakdown by the electrostatic discharge, charged carriers (60) are generated, and attracted by the Shockley diode (22). The base (54) of the trigger transistor (24) is biased during normal operations iwth a supply voltage, and during electrostatic discharges to a higher voltage by an inherent Zener diode (64). When normal power is applied to the integrated circuit (10), input latch-up immunity is enhanced, and when an electrostatic discharge appears at the input bond pad (12), the electrostatic discharge protection is enhanced.

Electrostatic discharge protection for semiconductor input devices

Protection against damage due to electrostatic discharge is provided by the addition of elongate conductor ballast resistor strips (18, 20, 22) formed in series with the transistor device (10). The material forming the conductor strips (18, 20, 22) includes a positive temperature coefficient, thereby offsetting the negative temperature coefficient of the semiconductor material forming the transistor (10). Plural conductor strips are arranged in parallel to reduce the overall resistance to the transistor (10). High current density areas are prevented by providing a plurality of sub-transistors (48) formed in plural individual moats (40-46). The individual current paths reduce the formation of filaments caused by the high concentrations of current in a small area.

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Kueing L Chen