Taiwan Semiconductor Manufacturing Comp. Ltd.

Kuei-Lun Lin

Jian-Hao Chen

Chi On Chui

Kuo-Feng Yu

Xiong-Fei Yu

Shan-Mei Liao

Yen-Ming Chen

Feng-Cheng Yang

Shih-Hao Lin

Hui-Chi Chen

Wen-Hung Huang

Chia-Wei Chen

Cheng-Hao Hou

Chia-Yuan Chang

Yung-Hsiang Chan

Chih-Yu Hsu

Yao-Teng Chuang

Yu-Chia Liang

Da-Yuan Lee

Chi-On Chui

Che-Hao Chang

Chia-Wei Hsu

Te-Yang Lai

Kun-Yu Lee

Tsung-Da Lin

Yen-Fu Chen

Yen-Jui Chiu

Weng Chang

Po-Ting Lin

In an embodiment, a semiconductor device is provided, which includes a first doped gate dielectric layer and a second doped gate dielectric layer, wherein the first doped gate dielectric layer and the second doped gate dielectric layer comprise a high-k material doped with a dipole dopant. The second doped gate dielectric layer has a second concentration of the first dipole dopant. The concentration of the dipole dopant in the first doped gate dielectric layer is greater than the concentration, and the concentration peak of the dipole dopant in the first doped gate dielectric layer is deeper than the concentration peak of the dipole dopant in the second doped gate dielectric layer. A first gate electrode over the first doped gate dielectric layer, and a second gate electrode over the second doped gate dielectric layer, the first gate electrode and the second gate electrode have a same width.

Semiconductor device having doped gate dielectric layer and method for forming the same

A method includes following steps. A first gate dielectric layer is deposited over a first semiconductor channel and a second semiconductor channel. A second gate dielectric layer is deposited over the first gate dielectric layer. A layer is formed over the second gate dielectric layer using atomic layer deposition (ALD) cycles each comprising sequentially performing a first pulse step for a first pulse time, a first purge step for a first purge time, a second pulse step for a second pulse time, and a second purge step for a second purge time. A ratio of the first purge time to the first pulse time is greater than a ratio of the second purge time to the second pulse time. The layer is patterned to expose a portion of the second gate dielectric layer. The exposed portion of the second gate dielectric layer is etched.

Formation of transistor gates

A semiconductor device includes a first semiconductor layer below a second semiconductor layer; first and second gate dielectric layers surrounding the first and the second semiconductor layers, respectively; and a gate electrode surrounding both the first and the second gate dielectric layers. The first gate dielectric layer has a first top section above the first semiconductor layer and a first bottom section below the first semiconductor layer. The second gate dielectric layer has a second top section above the second semiconductor layer and a second bottom section below the second semiconductor layer. The first top section has a first thickness. The second top section has a second thickness. The second thickness is greater than the first thickness.

Semiconductor device with non-conformal gate dielectric layers

In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.

Semiconductor device and method

A semiconductor device a method of forming the same are provided. The method includes forming a fin extending from a substrate and forming a gate dielectric layer along a top surface and sidewalls of the fin. A first thickness of the gate dielectric layer along the top surface of the fin is greater than a second thickness of the gate dielectric layer along the sidewalls of the fin.

Fin field effect transistor having conformal and non-conformal gate dielectric layers

A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Multi-layer high-k gate dielectric structure

A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The method includes depositing a gate dielectric layer over the insulating layer and in the wide trench and the narrow trench using an atomic layer deposition process. The method includes forming a gate electrode layer over the gate dielectric layer. The method includes removing the gate dielectric layer and the gate electrode layer outside of the wide trench and the narrow trench.

Method for forming semiconductor device structure with gate

A method includes providing first and second channel layers in NMOS and PMOS regions respectively of a substrate; depositing a first layer comprising hafnium oxide over the first and second channel layers; forming a first dipole pattern over the second channel layer and not over the first channel layer; driving a first metal from the first dipole pattern into the first layer by annealing; removing the first dipole pattern; depositing a second layer comprising hafnium oxide over the first layer and over the first and second channel layers; forming a second dipole pattern over the second layer and the first channel layer and not over the second channel layer; driving a second metal from the second dipole pattern into the second layer by annealing; removing the second dipole pattern; and depositing a third layer comprising hafnium oxide over the second layer and over the first and the second channel layers.

Triple layer high-k gate dielectric stack for workfunction engineering

Semiconductor device with non-conformal gate dieletric layers

A method comprises forming first and second fins each comprising alternately stacking first and second semiconductor layers; forming dummy gate structures over the first and second fins, and gate spacers on either side of the dummy gate structures; removing the dummy gate structures to form first and second gate trenches; removing the first semiconductor layers such that the second semiconductor layers are suspended in the first and second gate trenches; depositing a first dielectric layer around the second semiconductor layers and a second dielectric layer around the first dielectric layer; performing an ALD process to form a hard mask layer around the second dielectric layer, the ALD process comprising pulsing a first precursor for a first pulse time longer than about one second; patterning the hard mask layer; and etching a portion of the second gate dielectric layer in the second gate trench.

A semiconductor device includes a stack of semiconductor layers vertically arranged above a semiconductor base structure, a gate dielectric layer having portions each surrounding one of the semiconductor layers, and a gate electrode surrounding the gate dielectric layer. Each portion of the gate dielectric layer has a top section above the respective semiconductor layer and a bottom section below the semiconductor layer. The top section has a top thickness along a vertical direction perpendicular to a top surface of the semiconductor base structure; and the bottom section has a bottom thickness along the vertical direction. The top thickness is greater than the bottom thickness.

Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate structure over the substrate. The gate structure includes a high-k layer over the substrate, a shielding layer over the high-k layer, and an N-type work function metal layer over the shielding layer. In some embodiments, the shielding layer has a dielectric constant less than a dielectric constant of the high-k layer.

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Keelung, Taiwan

Kuei-Lun Lin